drm/radeon/cik: drop cg_update from dpm code
I'm not entirely sure this is required and it won't work with the dpm restructing anyway. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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68e3a092c1
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@ -171,8 +171,6 @@ extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
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struct atom_voltage_table *voltage_table);
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extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
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extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
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extern void cik_update_cg(struct radeon_device *rdev,
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u32 block, bool enable);
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static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
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struct atom_voltage_table_entry *voltage_table,
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@ -4561,13 +4559,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
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struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_UVD |
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RADEON_CG_BLOCK_HDP), false);
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if (ci_is_smc_running(rdev))
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return -EINVAL;
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if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
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@ -4689,13 +4680,6 @@ int ci_dpm_enable(struct radeon_device *rdev)
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ci_dpm_powergate_uvd(rdev, true);
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_UVD |
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RADEON_CG_BLOCK_HDP), true);
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ci_update_current_ps(rdev, boot_ps);
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return 0;
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@ -4706,12 +4690,6 @@ void ci_dpm_disable(struct radeon_device *rdev)
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struct ci_power_info *pi = ci_get_pi(rdev);
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struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_UVD |
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RADEON_CG_BLOCK_HDP), false);
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ci_dpm_powergate_uvd(rdev, false);
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if (!ci_is_smc_running(rdev))
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@ -4742,13 +4720,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
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struct radeon_ps *old_ps = &pi->current_rps;
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_UVD |
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RADEON_CG_BLOCK_HDP), false);
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ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
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if (pi->pcie_performance_request)
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ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
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@ -4804,13 +4775,6 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
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if (pi->pcie_performance_request)
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ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_MC |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_UVD |
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RADEON_CG_BLOCK_HDP), true);
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return 0;
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}
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@ -1126,11 +1126,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
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struct kv_power_info *pi = kv_get_pi(rdev);
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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ret = kv_process_firmware_header(rdev);
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if (ret) {
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DRM_ERROR("kv_process_firmware_header failed\n");
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@ -1238,11 +1233,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
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kv_dpm_powergate_vce(rdev, true);
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kv_dpm_powergate_uvd(rdev, true);
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), true);
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kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
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return ret;
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@ -1250,11 +1240,6 @@ int kv_dpm_enable(struct radeon_device *rdev)
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void kv_dpm_disable(struct radeon_device *rdev)
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{
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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kv_smc_bapm_enable(rdev, false);
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/* powerup blocks */
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@ -1779,11 +1764,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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/*struct radeon_ps *old_ps = &pi->current_rps;*/
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int ret;
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), false);
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if (pi->bapm_enable) {
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ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
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if (ret) {
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@ -1849,11 +1829,6 @@ int kv_dpm_set_power_state(struct radeon_device *rdev)
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}
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}
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cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
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RADEON_CG_BLOCK_SDMA |
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RADEON_CG_BLOCK_BIF |
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RADEON_CG_BLOCK_HDP), true);
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return 0;
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}
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