clk: exynos5440: register clocks using common clock framework
The Exynos5440 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>hifive-unleashed-5.1
Thomas Abraham
Kukjin Kim
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6e3ad26816
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f2585b1cce
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@ -0,0 +1,61 @@
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* Samsung Exynos5440 Clock Controller
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The Exynos5440 clock controller generates and supplies clock to various
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controllers within the Exynos5440 SoC.
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Required Properties:
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- comptible: should be "samsung,exynos5440-clock".
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume.
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[Core Clocks]
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Clock ID
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----------------------------
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xtal 1
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arm_clk 2
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[Peripheral Clock Gates]
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Clock ID
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----------------------------
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spi_baud 16
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pb0_250 17
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pr0_250 18
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pr1_250 19
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b_250 20
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b_125 21
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b_200 22
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sata 23
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usb 24
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gmac0 25
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cs250 26
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pb0_250_o 27
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pr0_250_o 28
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pr1_250_o 29
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b_250_o 30
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b_125_o 31
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b_200_o 32
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sata_o 33
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usb_o 34
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gmac0_o 35
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cs250_o 36
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Example: An example of a clock controller node is listed below.
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clock: clock-controller@0x10010000 {
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compatible = "samsung,exynos5440-clock";
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reg = <0x160000 0x10000>;
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#clock-cells = <1>;
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};
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@ -5,3 +5,4 @@
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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@ -0,0 +1,139 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Exynos5440 SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <plat/cpu.h>
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#include "clk.h"
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#include "clk-pll.h"
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#define CLKEN_OV_VAL 0xf8
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#define CPU_CLK_STATUS 0xfc
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#define MISC_DOUT1 0x558
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/*
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* Let each supported clock get a unique id. This id is used to lookup the clock
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* for device tree based platforms.
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*/
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enum exynos5440_clks {
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none, xtal, arm_clk,
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spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
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usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
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b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
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nr_clks,
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};
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/* parent clock name list */
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PNAME(mout_armclk_p) = { "cplla", "cpllb" };
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PNAME(mout_spi_p) = { "div125", "div200" };
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/* fixed rate clocks generated outside the soc */
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struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
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FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
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};
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/* fixed rate clocks */
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struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
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FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
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FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
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FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
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FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
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FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
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};
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/* fixed factor clocks */
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struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
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FFACTOR(none, "div250", "ppll", 1, 4, 0),
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FFACTOR(none, "div200", "ppll", 1, 5, 0),
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FFACTOR(none, "div125", "div250", 1, 2, 0),
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};
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/* mux clocks */
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struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
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MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
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MUX_A(arm_clk, "arm_clk", mout_armclk_p,
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CPU_CLK_STATUS, 0, 1, "armclk"),
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};
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/* divider clocks */
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struct samsung_div_clock exynos5440_div_clks[] __initdata = {
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DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
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};
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/* gate clocks */
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struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
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GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
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GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
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GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
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GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
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GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
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GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
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GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
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GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
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GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
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GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
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GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
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GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
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GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
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GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
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GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
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GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
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GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
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GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
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GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
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GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
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};
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static __initdata struct of_device_id ext_clk_match[] = {
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{ .compatible = "samsung,clock-xtal", .data = (void *)0, },
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{},
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};
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/* register exynos5440 clocks */
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void __init exynos5440_clk_init(struct device_node *np)
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{
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: failed to map clock controller registers,"
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" aborting clock initialization\n", __func__);
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return;
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}
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samsung_clk_init(np, reg_base, nr_clks, NULL, 0);
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samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
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samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
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samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
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samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
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ARRAY_SIZE(exynos5440_fixed_rate_clks));
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samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
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ARRAY_SIZE(exynos5440_fixed_factor_clks));
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samsung_clk_register_mux(exynos5440_mux_clks,
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ARRAY_SIZE(exynos5440_mux_clks));
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samsung_clk_register_div(exynos5440_div_clks,
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ARRAY_SIZE(exynos5440_div_clks));
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samsung_clk_register_gate(exynos5440_gate_clks,
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ARRAY_SIZE(exynos5440_gate_clks));
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pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
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pr_info("exynos5440 clock initialization complete\n");
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}
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CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
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