x86: make apic_32/64.c more like
except x2apic, detec_init_APIC, and calibrating_APIC_clock Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Yinghai Lu
Ingo Molnar
parent
3491998dd5
commit
f28c0ae21d
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@ -66,6 +66,9 @@ static int __init parse_lapic(char *arg)
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return 0;
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}
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early_param("lapic", parse_lapic);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
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static int enabled_via_apicbase;
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#endif
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#ifdef CONFIG_X86_64
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@ -131,9 +134,6 @@ static struct clock_event_device lapic_clockevent = {
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};
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static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
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static int enabled_via_apicbase;
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static unsigned long apic_phys;
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/*
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@ -240,6 +240,7 @@ void __cpuinit enable_NMI_through_LVT0(void)
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apic_write(APIC_LVT0, v);
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}
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#ifdef CONFIG_X86_32
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/**
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* get_physical_broadcast - Get number of physical broadcast IDs
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*/
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@ -247,6 +248,7 @@ int get_physical_broadcast(void)
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{
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return modern_apic() ? 0xff : 0xf;
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}
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#endif
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/**
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* lapic_get_maxlvt - get the maximum number of local vector table entries
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@ -1291,6 +1293,32 @@ no_apic:
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return -1;
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}
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#ifdef CONFIG_X86_64
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void __init early_init_lapic_mapping(void)
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{
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unsigned long phys_addr;
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/*
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* If no local APIC can be found then go out
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* : it means there is no mpatable and MADT
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*/
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if (!smp_found_config)
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return;
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phys_addr = mp_lapic_addr;
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set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
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apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
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APIC_BASE, phys_addr);
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/*
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* Fetch the APIC ID of the BSP in case we have a
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* default configuration (or the MP table is broken).
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*/
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boot_cpu_physical_apicid = read_apic_id();
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}
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#endif
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/**
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* init_apic_mappings - initialize APIC mappings
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*/
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@ -1308,8 +1336,8 @@ void __init init_apic_mappings(void)
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apic_phys = mp_lapic_addr;
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set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
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printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
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apic_phys);
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apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
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APIC_BASE, apic_phys);
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/*
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* Fetch the APIC ID of the BSP in case we have a
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@ -1317,14 +1345,12 @@ void __init init_apic_mappings(void)
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*/
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if (boot_cpu_physical_apicid == -1U)
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boot_cpu_physical_apicid = read_apic_id();
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}
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/*
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* This initializes the IO-APIC and APIC hardware if this is
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* a UP kernel.
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*/
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int apic_version[MAX_APICS];
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int __init APIC_init_uniprocessor(void)
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@ -1682,11 +1708,6 @@ static int lapic_resume(struct sys_device *dev)
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local_irq_save(flags);
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#ifdef CONFIG_X86_64
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if (x2apic)
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enable_x2apic();
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else
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#endif
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{
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/*
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* Make sure the APICBASE points to the right address
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@ -1770,7 +1791,87 @@ static void apic_pm_activate(void) { }
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#endif /* CONFIG_PM */
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#ifdef CONFIG_X86_64
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/*
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* apic_is_clustered_box() -- Check if we can expect good TSC
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*
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* Thus far, the major user of this is IBM's Summit2 series:
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*
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* Clustered boxes may have unsynced TSC problems if they are
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* multi-chassis. Use available data to take a good guess.
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* If in doubt, go HPET.
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*/
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__cpuinit int apic_is_clustered_box(void)
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{
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int i, clusters, zeros;
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unsigned id;
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u16 *bios_cpu_apicid;
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DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
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/*
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* there is not this kind of box with AMD CPU yet.
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* Some AMD box with quadcore cpu and 8 sockets apicid
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* will be [4, 0x23] or [8, 0x27] could be thought to
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* vsmp box still need checking...
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*/
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
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return 0;
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bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
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bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
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for (i = 0; i < NR_CPUS; i++) {
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/* are we being called early in kernel startup? */
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if (bios_cpu_apicid) {
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id = bios_cpu_apicid[i];
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}
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else if (i < nr_cpu_ids) {
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if (cpu_present(i))
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id = per_cpu(x86_bios_cpu_apicid, i);
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else
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continue;
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}
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else
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break;
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if (id != BAD_APICID)
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__set_bit(APIC_CLUSTERID(id), clustermap);
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}
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/* Problem: Partially populated chassis may not have CPUs in some of
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* the APIC clusters they have been allocated. Only present CPUs have
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* x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
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* Since clusters are allocated sequentially, count zeros only if
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* they are bounded by ones.
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*/
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clusters = 0;
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zeros = 0;
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for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
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if (test_bit(i, clustermap)) {
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clusters += 1 + zeros;
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zeros = 0;
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} else
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++zeros;
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}
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/* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
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* not guaranteed to be synced between boards
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*/
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if (is_vsmp_box() && clusters > 1)
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return 1;
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/*
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* If clusters > 2, then should be multi-chassis.
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* May have to revisit this when multi-core + hyperthreaded CPUs come
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* out, but AFAIK this will work even for them.
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*/
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return (clusters > 2);
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}
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#endif
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/*
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* APIC command line parameters
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*/
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static int __init setup_disableapic(char *arg)
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{
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disable_apic = 1;
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@ -69,6 +69,9 @@ static int __init parse_lapic(char *arg)
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return 0;
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}
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early_param("lapic", parse_lapic);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
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static int enabled_via_apicbase;
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#endif
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#ifdef CONFIG_X86_64
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@ -1279,6 +1282,7 @@ static int __init detect_init_APIC(void)
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return 0;
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}
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#ifdef CONFIG_X86_64
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void __init early_init_lapic_mapping(void)
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{
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unsigned long phys_addr;
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@ -1302,6 +1306,7 @@ void __init early_init_lapic_mapping(void)
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*/
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boot_cpu_physical_apicid = read_apic_id();
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}
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#endif
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/**
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* init_apic_mappings - initialize APIC mappings
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@ -1334,7 +1339,8 @@ void __init init_apic_mappings(void)
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* Fetch the APIC ID of the BSP in case we have a
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* default configuration (or the MP table is broken).
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*/
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boot_cpu_physical_apicid = read_apic_id();
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if (boot_cpu_physical_apicid == -1U)
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boot_cpu_physical_apicid = read_apic_id();
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}
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/*
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@ -1782,6 +1788,7 @@ static void apic_pm_activate(void) { }
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#endif /* CONFIG_PM */
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#ifdef CONFIG_X86_64
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/*
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* apic_is_clustered_box() -- Check if we can expect good TSC
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*
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@ -1857,6 +1864,7 @@ __cpuinit int apic_is_clustered_box(void)
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*/
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return (clusters > 2);
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}
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#endif
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/*
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* APIC command line parameters
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