drm/i915: Update some flush helpers to take request structures
Updated intel_emit_post_sync_nonzero_flush(), gen7_render_ring_cs_stall_wa() and gen8_emit_pipe_control() to take requests instead of rings. For: VIZ-5115 Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Tomas Elf <tomas.elf@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -214,8 +214,9 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
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* really our business. That leaves only stall at scoreboard.
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*/
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static int
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intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
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intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
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{
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struct intel_engine_cs *ring = req->ring;
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u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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int ret;
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@ -258,7 +259,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
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int ret;
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/* Force SNB workarounds for PIPE_CONTROL flushes */
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ret = intel_emit_post_sync_nonzero_flush(ring);
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ret = intel_emit_post_sync_nonzero_flush(req);
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if (ret)
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return ret;
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@ -302,8 +303,9 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
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}
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static int
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gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
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gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
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{
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struct intel_engine_cs *ring = req->ring;
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int ret;
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ret = intel_ring_begin(ring, 4);
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@ -366,7 +368,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
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/* Workaround: we must issue a pipe_control with CS-stall bit
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* set before a pipe_control command that has the state cache
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* invalidate bit set. */
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gen7_render_ring_cs_stall_wa(ring);
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gen7_render_ring_cs_stall_wa(req);
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}
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ret = intel_ring_begin(ring, 4);
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@ -383,9 +385,10 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
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}
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static int
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gen8_emit_pipe_control(struct intel_engine_cs *ring,
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gen8_emit_pipe_control(struct drm_i915_gem_request *req,
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u32 flags, u32 scratch_addr)
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{
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struct intel_engine_cs *ring = req->ring;
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int ret;
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ret = intel_ring_begin(ring, 6);
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@ -407,9 +410,8 @@ static int
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gen8_render_ring_flush(struct drm_i915_gem_request *req,
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u32 invalidate_domains, u32 flush_domains)
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{
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struct intel_engine_cs *ring = req->ring;
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u32 flags = 0;
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u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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int ret;
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flags |= PIPE_CONTROL_CS_STALL;
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@ -429,7 +431,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
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ret = gen8_emit_pipe_control(ring,
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ret = gen8_emit_pipe_control(req,
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_STALL_AT_SCOREBOARD,
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0);
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@ -437,7 +439,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
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return ret;
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}
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return gen8_emit_pipe_control(ring, flags, scratch_addr);
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return gen8_emit_pipe_control(req, flags, scratch_addr);
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}
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static void ring_write_tail(struct intel_engine_cs *ring,
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