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powerpc/tm: update comment about interrupt re-entrancy 

Since the system reset interrupt began to use its own stack, and
machine check interrupts have done so for some time, r1 can be
changed without clearing MSR[RI], provided no other interrupts
(including SLB misses) are taken.

MSR[RI] does have to be cleared when using SCRATCH0, however.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
alistair/sunxi64-5.4-dsi
Nicholas Piggin 2019-06-28 15:33:32 +10:00 committed by Michael Ellerman
parent d7fb34c704
commit f30a5e68f0
1 changed files with 2 additions and 2 deletions
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4
arch/powerpc/kernel/tm.S
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@ -148,7 +148,7 @@ _GLOBAL(tm_reclaim)
/* Stash the stack pointer away for use after reclaim */
std r1, PACAR1(r13)
/* Clear MSR RI since we are about to change r1, EE is already off. */
/* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
li r5, 0
mtmsrd r5, 1
@ -474,7 +474,7 @@ restore_gprs:
REST_GPR(7, r7)
/* Clear MSR RI since we are about to change r1. EE is already off */
/* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
li r5, 0
mtmsrd r5, 1