ARM: mvebu: use GIC_{SPI,PPI} in Armada 375/38x DTs
Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts, use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to clarify the Device Tree code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>hifive-unleashed-5.1
Thomas Petazzoni
Jason Cooper
parent
a2be1561a3
commit
f327d43da1
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@ -12,6 +12,7 @@
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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@ -129,7 +130,7 @@
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <1 13 0x301>;
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interrupts = <GIC_PPI 13 0x301>;
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clocks = <&coreclk 2>;
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};
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@ -148,7 +149,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <0 1 0x4>;
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interrupts = <GIC_SPI 1 0x4>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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@ -159,7 +160,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <0 63 0x4>;
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interrupts = <GIC_SPI 63 0x4>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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@ -169,7 +170,7 @@
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 2 0x4>;
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interrupts = <GIC_SPI 2 0x4>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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@ -180,7 +181,7 @@
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 3 0x4>;
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interrupts = <GIC_SPI 3 0x4>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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@ -190,7 +191,7 @@
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <0 12 4>;
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interrupts = <GIC_SPI 12 4>;
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reg-io-width = <1>;
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status = "disabled";
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};
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@ -199,7 +200,7 @@
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <0 13 4>;
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interrupts = <GIC_SPI 13 4>;
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reg-io-width = <1>;
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status = "disabled";
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};
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@ -248,8 +249,8 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 53 0x4>, <0 54 0x4>,
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<0 55 0x4>, <0 56 0x4>;
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interrupts = <GIC_SPI 53 0x4>, <GIC_SPI 54 0x4>,
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<GIC_SPI 55 0x4>, <GIC_SPI 56 0x4>;
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};
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gpio1: gpio@18140 {
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@ -260,8 +261,8 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 58 0x4>, <0 59 0x4>,
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<0 60 0x4>, <0 61 0x4>;
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interrupts = <GIC_SPI 58 0x4>, <GIC_SPI 59 0x4>,
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<GIC_SPI 60 0x4>, <GIC_SPI 61 0x4>;
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};
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gpio2: gpio@18180 {
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@ -272,7 +273,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 62 0x4>;
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interrupts = <GIC_SPI 62 0x4>;
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};
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system-controller@18200 {
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@ -299,16 +300,16 @@
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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interrupts = <1 15 0x4>;
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interrupts = <GIC_PPI 15 0x4>;
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};
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timer@20300 {
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compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts-extended = <&gic 0 8 4>,
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<&gic 0 9 4>,
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<&gic 0 10 4>,
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<&gic 0 11 4>,
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interrupts-extended = <&gic GIC_SPI 8 4>,
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<&gic GIC_SPI 9 4>,
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<&gic GIC_SPI 10 4>,
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<&gic GIC_SPI 11 4>,
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<&mpic 5>,
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<&mpic 6>;
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clocks = <&coreclk 0>;
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@ -322,12 +323,12 @@
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status = "okay";
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xor00 {
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interrupts = <0 22 0x4>;
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interrupts = <GIC_SPI 22 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <0 23 0x4>;
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interrupts = <GIC_SPI 23 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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@ -342,12 +343,12 @@
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status = "okay";
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xor10 {
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interrupts = <0 65 0x4>;
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interrupts = <GIC_SPI 65 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <0 66 0x4>;
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interrupts = <GIC_SPI 66 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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@ -357,7 +358,7 @@
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sata@a0000 {
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compatible = "marvell,orion-sata";
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reg = <0xa0000 0x5000>;
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interrupts = <0 26 0x4>;
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interrupts = <GIC_SPI 26 0x4>;
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clocks = <&gateclk 14>, <&gateclk 20>;
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clock-names = "0", "1";
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status = "disabled";
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@ -368,7 +369,7 @@
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <0 84 0x4>;
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interrupts = <GIC_SPI 84 0x4>;
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clocks = <&gateclk 11>;
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status = "disabled";
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};
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@ -376,7 +377,7 @@
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mvsdio@d4000 {
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compatible = "marvell,orion-sdio";
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reg = <0xd4000 0x200>;
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interrupts = <0 25 0x4>;
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interrupts = <GIC_SPI 25 0x4>;
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clocks = <&gateclk 17>;
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bus-width = <4>;
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cap-sdio-irq;
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@ -429,7 +430,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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@ -446,7 +447,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 6>;
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@ -70,7 +70,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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@ -88,7 +88,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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@ -106,7 +106,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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@ -81,7 +81,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 29 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 29 0x4>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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@ -99,7 +99,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 33 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 33 0x4>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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@ -117,7 +117,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 70 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 70 0x4>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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@ -138,7 +138,7 @@
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 71 0x4>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 71 0x4>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 7>;
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@ -13,6 +13,7 @@
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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@ -109,7 +110,7 @@
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <1 13 0x301>;
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interrupts = <GIC_PPI 13 0x301>;
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clocks = <&coreclk 2>;
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};
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@ -128,7 +129,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <0 1 0x4>;
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interrupts = <GIC_SPI 1 0x4>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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@ -139,7 +140,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <0 63 0x4>;
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interrupts = <GIC_SPI 63 0x4>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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@ -149,7 +150,7 @@
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 2 0x4>;
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interrupts = <GIC_SPI 2 0x4>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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@ -160,7 +161,7 @@
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 3 0x4>;
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interrupts = <GIC_SPI 3 0x4>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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@ -170,7 +171,7 @@
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <0 12 4>;
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interrupts = <GIC_SPI 12 4>;
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reg-io-width = <1>;
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status = "disabled";
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};
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@ -179,7 +180,7 @@
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <0 13 4>;
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interrupts = <GIC_SPI 13 4>;
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reg-io-width = <1>;
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status = "disabled";
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};
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@ -197,8 +198,8 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 53 0x4>, <0 54 0x4>,
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<0 55 0x4>, <0 56 0x4>;
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interrupts = <GIC_SPI 53 0x4>, <GIC_SPI 54 0x4>,
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<GIC_SPI 55 0x4>, <GIC_SPI 56 0x4>;
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};
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gpio1: gpio@18140 {
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@ -209,8 +210,8 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 58 0x4>, <0 59 0x4>,
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<0 60 0x4>, <0 61 0x4>;
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interrupts = <GIC_SPI 58 0x4>, <GIC_SPI 59 0x4>,
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<GIC_SPI 60 0x4>, <GIC_SPI 61 0x4>;
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};
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system-controller@18200 {
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@ -244,17 +245,17 @@
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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interrupts = <1 15 0x4>;
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interrupts = <GIC_PPI 15 0x4>;
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};
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timer@20300 {
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compatible = "marvell,armada-380-timer",
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"marvell,armada-xp-timer";
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts-extended = <&gic 0 8 4>,
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<&gic 0 9 4>,
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<&gic 0 10 4>,
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<&gic 0 11 4>,
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interrupts-extended = <&gic GIC_SPI 8 4>,
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<&gic GIC_SPI 9 4>,
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<&gic GIC_SPI 10 4>,
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<&gic GIC_SPI 11 4>,
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<&mpic 5>,
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<&mpic 6>;
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clocks = <&coreclk 2>, <&refclk>;
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@ -285,12 +286,12 @@
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status = "okay";
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xor00 {
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interrupts = <0 22 0x4>;
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interrupts = <GIC_SPI 22 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <0 23 0x4>;
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interrupts = <GIC_SPI 23 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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@ -305,12 +306,12 @@
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status = "okay";
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xor10 {
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interrupts = <0 65 0x4>;
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interrupts = <GIC_SPI 65 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <0 66 0x4>;
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interrupts = <GIC_SPI 66 0x4>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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