crypto: arm/aes-ce - work around Cortex-A57/A72 silion errata
ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are affected by silicon errata #1742098 and #1655431, respectively, where the second instruction of a AES instruction pair may execute twice if an interrupt is taken right after the first instruction consumes an input register of which a single 32-bit lane has been updated the last time it was modified. This is not such a rare occurrence as it may seem: in counter mode, only the least significant 32-bit word is incremented in the absence of a carry, which makes our counter mode implementation susceptible to these errata. So let's shuffle the counter assignments around a bit so that the most recent updates when the AES instruction pair executes are 128-bit wide. [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice Cc: <stable@vger.kernel.org> # v5.4+ Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>zero-sugar-mainline-defconfig
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@ -386,20 +386,32 @@ ENTRY(ce_aes_ctr_encrypt)
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.Lctrloop4x:
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.Lctrloop4x:
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subs r4, r4, #4
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subs r4, r4, #4
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bmi .Lctr1x
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bmi .Lctr1x
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add r6, r6, #1
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/*
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* NOTE: the sequence below has been carefully tweaked to avoid
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* a silicon erratum that exists in Cortex-A57 (#1742098) and
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* Cortex-A72 (#1655431) cores, where AESE/AESMC instruction pairs
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* may produce an incorrect result if they take their input from a
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* register of which a single 32-bit lane has been updated the last
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* time it was modified. To work around this, the lanes of registers
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* q0-q3 below are not manipulated individually, and the different
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* counter values are prepared by successive manipulations of q7.
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*/
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add ip, r6, #1
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vmov q0, q7
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vmov q0, q7
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rev ip, ip
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add lr, r6, #2
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vmov s31, ip @ set lane 3 of q1 via q7
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add ip, r6, #3
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rev lr, lr
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vmov q1, q7
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vmov q1, q7
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rev ip, r6
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vmov s31, lr @ set lane 3 of q2 via q7
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add r6, r6, #1
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rev ip, ip
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vmov q2, q7
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vmov q2, q7
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vmov s7, ip
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vmov s31, ip @ set lane 3 of q3 via q7
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rev ip, r6
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add r6, r6, #4
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add r6, r6, #1
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vmov q3, q7
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vmov q3, q7
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vmov s11, ip
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rev ip, r6
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add r6, r6, #1
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vmov s15, ip
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vld1.8 {q4-q5}, [r1]!
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vld1.8 {q4-q5}, [r1]!
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vld1.8 {q6}, [r1]!
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vld1.8 {q6}, [r1]!
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vld1.8 {q15}, [r1]!
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vld1.8 {q15}, [r1]!
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