cpufreq: tegra: Add support for Tegra210
This uses the DFLL clock support to enable CPU frequency scaling on Tegra210. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdl6MTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoX/LD/9mh+TFN9pefVv3TlXn08c6zyayZzDp 0YpUQMXktqMwYrLsYcwL7O7KEhwEClMDrNVNSuPOCH564GxonCud6AwMPqgpiEhf 5OJuMndnDlM1AGKzPYU6JU2n8C1YafoKBLaN/wZ4riwTw9mfXXJoJnG+D7Kwu+/6 2CwqmDBDMTOhlXtb7hyyfuLbZTP+0TKbDQdQpBlFgs9BFjs/2fKPbTCP75cD0RM1 2eVSlwaRBEMpsLQHZ5VZIxg2VcFqa79c1eB6pgZ2Hyn+BSae4F+i9N/DIjquiav4 hplbC/lr3AOMWtIx6V18wrS57qKGU28K9WuJeMfCpblMZrTYmNE96RghzMxP+5Zw gaAurj12dE+Ie5jfqzW/aW9ktJbX3rbEhrCDqly3H67K2v27G5Vstf1SssDhk7wy YF9KKFI5qjzVn0Bo8xcBukEfePQ2AjNeGMWrwWi4h53XvfyXcCSKbwY9DvcgocEH e2gUrCtyu/KWwV0r+6txw5UlZVuWI8SJpRhMv+En6F/tls/sIDB34PP0ubc/ZOKa Ehnb4E+uJfCxujsbpvpRIjKosTPD7R52X1Stcw3lcxsxOF3pE2DQhXVkAC22jfT/ qKmaDNq6Cdm8kc5CuwqHTY5CygvFRC6cu/jT4qouWWyo3WFDQ1WDAasGER7TXvsK tMIjAMGQOxvn5Q== =pSIK -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers cpufreq: tegra: Add support for Tegra210 This uses the DFLL clock support to enable CPU frequency scaling on Tegra210. * tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: cpufreq: dt-platdev: add Tegra210 to blacklist cpufreq: tegra124: extend to support Tegra210 cpufreq: tegra124: do not handle the CPU rail Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
f35635a6b7
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@ -272,8 +272,8 @@ config ARM_TEGRA20_CPUFREQ
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This adds the CPUFreq driver support for Tegra20 SOCs.
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This adds the CPUFreq driver support for Tegra20 SOCs.
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config ARM_TEGRA124_CPUFREQ
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config ARM_TEGRA124_CPUFREQ
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tristate "Tegra124 CPUFreq support"
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bool "Tegra124 CPUFreq support"
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depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR
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depends on ARCH_TEGRA && CPUFREQ_DT
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default y
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default y
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help
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help
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This adds the CPUFreq driver support for Tegra124 SOCs.
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This adds the CPUFreq driver support for Tegra124 SOCs.
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@ -119,6 +119,7 @@ static const struct of_device_id blacklist[] __initconst = {
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{ .compatible = "mediatek,mt8176", },
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{ .compatible = "mediatek,mt8176", },
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{ .compatible = "nvidia,tegra124", },
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{ .compatible = "nvidia,tegra124", },
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{ .compatible = "nvidia,tegra210", },
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{ .compatible = "qcom,apq8096", },
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{ .compatible = "qcom,apq8096", },
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{ .compatible = "qcom,msm8996", },
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{ .compatible = "qcom,msm8996", },
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@ -22,11 +22,9 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/types.h>
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#include <linux/types.h>
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struct tegra124_cpufreq_priv {
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struct tegra124_cpufreq_priv {
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struct regulator *vdd_cpu_reg;
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struct clk *cpu_clk;
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struct clk *cpu_clk;
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struct clk *pllp_clk;
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struct clk *pllp_clk;
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struct clk *pllx_clk;
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struct clk *pllx_clk;
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@ -60,14 +58,6 @@ out:
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return ret;
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return ret;
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}
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}
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static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
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{
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clk_set_parent(priv->cpu_clk, priv->pllp_clk);
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clk_disable_unprepare(priv->dfll_clk);
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regulator_sync_voltage(priv->vdd_cpu_reg);
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clk_set_parent(priv->cpu_clk, priv->pllx_clk);
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}
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static int tegra124_cpufreq_probe(struct platform_device *pdev)
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static int tegra124_cpufreq_probe(struct platform_device *pdev)
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{
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{
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struct tegra124_cpufreq_priv *priv;
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struct tegra124_cpufreq_priv *priv;
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@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
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if (!np)
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if (!np)
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return -ENODEV;
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return -ENODEV;
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priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
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if (IS_ERR(priv->vdd_cpu_reg)) {
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ret = PTR_ERR(priv->vdd_cpu_reg);
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goto out_put_np;
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}
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priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
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priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
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if (IS_ERR(priv->cpu_clk)) {
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if (IS_ERR(priv->cpu_clk)) {
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ret = PTR_ERR(priv->cpu_clk);
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ret = PTR_ERR(priv->cpu_clk);
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goto out_put_vdd_cpu_reg;
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goto out_put_np;
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}
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}
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priv->dfll_clk = of_clk_get_by_name(np, "dfll");
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priv->dfll_clk = of_clk_get_by_name(np, "dfll");
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@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
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platform_device_register_full(&cpufreq_dt_devinfo);
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platform_device_register_full(&cpufreq_dt_devinfo);
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if (IS_ERR(priv->cpufreq_dt_pdev)) {
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if (IS_ERR(priv->cpufreq_dt_pdev)) {
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ret = PTR_ERR(priv->cpufreq_dt_pdev);
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ret = PTR_ERR(priv->cpufreq_dt_pdev);
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goto out_switch_to_pllx;
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goto out_put_pllp_clk;
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}
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}
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platform_set_drvdata(pdev, priv);
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platform_set_drvdata(pdev, priv);
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return 0;
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return 0;
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out_switch_to_pllx:
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tegra124_cpu_switch_to_pllx(priv);
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out_put_pllp_clk:
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out_put_pllp_clk:
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clk_put(priv->pllp_clk);
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clk_put(priv->pllp_clk);
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out_put_pllx_clk:
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out_put_pllx_clk:
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@ -146,34 +128,15 @@ out_put_dfll_clk:
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clk_put(priv->dfll_clk);
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clk_put(priv->dfll_clk);
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out_put_cpu_clk:
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out_put_cpu_clk:
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clk_put(priv->cpu_clk);
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clk_put(priv->cpu_clk);
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out_put_vdd_cpu_reg:
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regulator_put(priv->vdd_cpu_reg);
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out_put_np:
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out_put_np:
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of_node_put(np);
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of_node_put(np);
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return ret;
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return ret;
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}
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}
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static int tegra124_cpufreq_remove(struct platform_device *pdev)
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{
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struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
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platform_device_unregister(priv->cpufreq_dt_pdev);
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tegra124_cpu_switch_to_pllx(priv);
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clk_put(priv->pllp_clk);
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clk_put(priv->pllx_clk);
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clk_put(priv->dfll_clk);
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clk_put(priv->cpu_clk);
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regulator_put(priv->vdd_cpu_reg);
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return 0;
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}
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static struct platform_driver tegra124_cpufreq_platdrv = {
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static struct platform_driver tegra124_cpufreq_platdrv = {
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.driver.name = "cpufreq-tegra124",
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.driver.name = "cpufreq-tegra124",
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.probe = tegra124_cpufreq_probe,
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.probe = tegra124_cpufreq_probe,
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.remove = tegra124_cpufreq_remove,
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};
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};
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static int __init tegra_cpufreq_init(void)
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static int __init tegra_cpufreq_init(void)
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@ -181,7 +144,8 @@ static int __init tegra_cpufreq_init(void)
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int ret;
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int ret;
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struct platform_device *pdev;
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struct platform_device *pdev;
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if (!of_machine_is_compatible("nvidia,tegra124"))
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if (!(of_machine_is_compatible("nvidia,tegra124") ||
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of_machine_is_compatible("nvidia,tegra210")))
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return -ENODEV;
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return -ENODEV;
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/*
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/*
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