Revert "net/ucc_geth: Add SGMII support for UEC GETH driver"
This reverts commit047584ce94
. This patch meshes badly with "net: Rework ucc_geth driver to use of_mdio infrastructure" (0b9da337dc
). Since most of the patch needs to be reworked, it is clearer to revert the patch and then apply the corrected version Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -668,8 +668,6 @@ struct ucc_slow_pram {
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#define UCC_GETH_UPSMR_RMM 0x00001000
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#define UCC_GETH_UPSMR_CAM 0x00000400
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#define UCC_GETH_UPSMR_BRO 0x00000200
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#define UCC_GETH_UPSMR_SMM 0x00000080
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#define UCC_GETH_UPSMR_SGMM 0x00000020
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/* UCC Transmit On Demand Register (UTODR) */
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#define UCC_SLOW_TOD 0x8000
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
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* Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
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*
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* Author: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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@ -65,8 +65,6 @@
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static DEFINE_SPINLOCK(ugeth_lock);
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static void uec_configure_serdes(struct net_device *dev);
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static struct {
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u32 msg_enable;
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} debug = { -1 };
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@ -1412,9 +1410,6 @@ static int adjust_enet_interface(struct ucc_geth_private *ugeth)
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(ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
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upsmr |= UCC_GETH_UPSMR_TBIM;
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}
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if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
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upsmr |= UCC_GETH_UPSMR_SGMM;
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out_be32(&uf_regs->upsmr, upsmr);
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/* Disable autonegotiation in tbi mode, because by default it
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@ -1559,9 +1554,6 @@ static int init_phy(struct net_device *dev)
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return -ENODEV;
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}
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if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
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uec_configure_serdes(dev);
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phydev->supported &= (ADVERTISED_10baseT_Half |
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ADVERTISED_10baseT_Full |
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ADVERTISED_100baseT_Half |
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@ -1577,41 +1569,7 @@ static int init_phy(struct net_device *dev)
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return 0;
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}
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/* Initialize TBI PHY interface for communicating with the
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* SERDES lynx PHY on the chip. We communicate with this PHY
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* through the MDIO bus on each controller, treating it as a
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* "normal" PHY at the address found in the UTBIPA register. We assume
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* that the UTBIPA register is valid. Either the MDIO bus code will set
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* it to a value that doesn't conflict with other PHYs on the bus, or the
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* value doesn't matter, as there are no other PHYs on the bus.
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*/
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static void uec_configure_serdes(struct net_device *dev)
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{
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struct ucc_geth_private *ugeth = netdev_priv(dev);
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if (!ugeth->tbiphy) {
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printk(KERN_WARNING "SGMII mode requires that the device "
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"tree specify a tbi-handle\n");
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return;
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}
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/*
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* If the link is already up, we must already be ok, and don't need to
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* configure and reset the TBI<->SerDes link. Maybe U-Boot configured
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* everything for us? Resetting it takes the link down and requires
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* several seconds for it to come back.
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*/
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if (phy_read(ugeth->tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
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return;
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/* Single clk mode, mii mode off(for serdes communication) */
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phy_write(ugeth->tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
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phy_write(ugeth->tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
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phy_write(ugeth->tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
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}
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static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
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{
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@ -3565,8 +3523,6 @@ static phy_interface_t to_phy_interface(const char *phy_connection_type)
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return PHY_INTERFACE_MODE_RGMII_RXID;
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if (strcasecmp(phy_connection_type, "rtbi") == 0)
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return PHY_INTERFACE_MODE_RTBI;
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if (strcasecmp(phy_connection_type, "sgmii") == 0)
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return PHY_INTERFACE_MODE_SGMII;
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return PHY_INTERFACE_MODE_MII;
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}
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@ -3611,7 +3567,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
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PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_SGMII,
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};
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ugeth_vdbg("%s: IN", __func__);
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@ -3727,7 +3682,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_TBI:
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case PHY_INTERFACE_MODE_RTBI:
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case PHY_INTERFACE_MODE_SGMII:
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max_speed = SPEED_1000;
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break;
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default:
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@ -3802,37 +3756,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma
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ugeth->ndev = dev;
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ugeth->node = np;
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/* Find the TBI PHY. If it's not there, we don't support SGMII */
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ph = of_get_property(np, "tbi-handle", NULL);
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if (ph) {
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struct device_node *tbi = of_find_node_by_phandle(*ph);
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struct of_device *ofdev;
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struct mii_bus *bus;
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const unsigned int *id;
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if (!tbi)
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return 0;
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mdio = of_get_parent(tbi);
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if (!mdio)
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return 0;
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ofdev = of_find_device_by_node(mdio);
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of_node_put(mdio);
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id = of_get_property(tbi, "reg", NULL);
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if (!id)
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return 0;
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of_node_put(tbi);
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bus = dev_get_drvdata(&ofdev->dev);
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if (!bus)
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return 0;
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ugeth->tbiphy = bus->phy_map[*id];
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}
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return 0;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
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* Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
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*
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* Author: Shlomi Gridish <gridish@freescale.com>
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*
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@ -193,31 +193,6 @@ struct ucc_geth {
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#define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
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#define ENET_TBI_MII_TBICON 0x11 /* TBI control */
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/* TBI MDIO register bit fields*/
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#define TBISR_LSTATUS 0x0004
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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#define TBICR_ANEG_ENABLE 0x1000
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#define TBICR_RESTART_ANEG 0x0200
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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#define TBIANA_SETTINGS ( \
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TBIANA_ASYMMETRIC_PAUSE \
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| TBIANA_SYMMETRIC_PAUSE \
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| TBIANA_FULL_DUPLEX \
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)
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#define TBICR_SETTINGS ( \
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TBICR_PHY_RESET \
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| TBICR_ANEG_ENABLE \
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| TBICR_FULL_DUPLEX \
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| TBICR_SPEED1_SET \
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)
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/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
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#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
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Rx */
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@ -1213,7 +1188,6 @@ struct ucc_geth_private {
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struct ugeth_mii_info *mii_info;
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struct phy_device *phydev;
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struct phy_device *tbiphy;
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phy_interface_t phy_interface;
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int max_speed;
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uint32_t msg_enable;
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