drm/i915/execlists: Reorder execlists register enabling
Empirically we restart following a GPU reset more successfully if we call lrc_init_hws() (which contains a posting read) last. (The failure mode that was observed was that breadcrumb writes into the HWS from the recovered requests went astray leading to the context-switch maintaining forward progress, but the requests not being retired/completed.) For clarity, lrc_init_hws() is inlined (and the unused function then removed). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170105153023.30575-3-chris@chris-wilson.co.uk
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@ -1335,15 +1335,6 @@ out:
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return ret;
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return ret;
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}
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}
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static void lrc_init_hws(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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I915_WRITE(RING_HWS_PGA(engine->mmio_base),
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engine->status_page.ggtt_offset);
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POSTING_READ(RING_HWS_PGA(engine->mmio_base));
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}
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static int gen8_init_common_ring(struct intel_engine_cs *engine)
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static int gen8_init_common_ring(struct intel_engine_cs *engine)
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{
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_private *dev_priv = engine->i915;
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@ -1353,20 +1344,19 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
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if (ret)
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if (ret)
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return ret;
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return ret;
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lrc_init_hws(engine);
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intel_engine_reset_breadcrumbs(engine);
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intel_engine_reset_breadcrumbs(engine);
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intel_engine_init_hangcheck(engine);
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I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
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I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
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I915_WRITE(RING_MODE_GEN7(engine),
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I915_WRITE(RING_MODE_GEN7(engine),
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_MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
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_MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
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_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
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_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
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I915_WRITE(RING_HWS_PGA(engine->mmio_base),
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engine->status_page.ggtt_offset);
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POSTING_READ(RING_HWS_PGA(engine->mmio_base));
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DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
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DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
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intel_engine_init_hangcheck(engine);
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/* After a GPU reset, we may have requests to replay */
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/* After a GPU reset, we may have requests to replay */
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if (!execlists_elsp_idle(engine)) {
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if (!execlists_elsp_idle(engine)) {
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engine->execlist_port[0].count = 0;
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engine->execlist_port[0].count = 0;
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