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drm/i915/execlists: Tidy enabling execlists 

Move the register settings for enabling execlists into its own function
for clarity.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180102151235.3949-18-chris@chris-wilson.co.uk
hifive-unleashed-5.1
Chris Wilson 2018-01-02 15:12:34 +00:00
parent 693cfbf058
commit f3c9d40757
1 changed files with 14 additions and 8 deletions
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22
drivers/gpu/drm/i915/intel_lrc.c
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@ -1469,9 +1469,20 @@ static u8 gtiir[] = {
[VECS] = 3,
};
static int gen8_init_common_ring(struct intel_engine_cs *engine)
static void enable_execlists(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
I915_WRITE(RING_MODE_GEN7(engine),
_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
}
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
int ret;
@ -1482,13 +1493,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
intel_engine_reset_breadcrumbs(engine);
intel_engine_init_hangcheck(engine);
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
I915_WRITE(RING_MODE_GEN7(engine),
_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
enable_execlists(engine);
DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
@ -1915,6 +1920,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
intel_engine_cleanup_common(engine);
lrc_destroy_wa_ctx(engine);
engine->i915 = NULL;
dev_priv->engine[engine->id] = NULL;
kfree(engine);