Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
This commit is contained in:
Linus Torvalds
commit
f44702f490
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@ -403,12 +403,3 @@ EXPORT_SYMBOL(xor_vis_4);
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EXPORT_SYMBOL(xor_vis_5);
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EXPORT_SYMBOL(prom_palette);
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/* memory barriers */
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EXPORT_SYMBOL(mb);
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EXPORT_SYMBOL(rmb);
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EXPORT_SYMBOL(wmb);
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EXPORT_SYMBOL(membar_storeload);
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EXPORT_SYMBOL(membar_storeload_storestore);
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EXPORT_SYMBOL(membar_storeload_loadload);
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EXPORT_SYMBOL(membar_storestore_loadstore);
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@ -12,7 +12,7 @@ lib-y := PeeCeeI.o copy_page.o clear_page.o strlen.o strncmp.o \
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U1memcpy.o U1copy_from_user.o U1copy_to_user.o \
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U3memcpy.o U3copy_from_user.o U3copy_to_user.o U3patch.o \
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copy_in_user.o user_fixup.o memmove.o \
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mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o mb.o
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mcount.o ipcsum.o rwsem.o xor.o find_bit.o delay.o
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lib-$(CONFIG_DEBUG_SPINLOCK) += debuglocks.o
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lib-$(CONFIG_HAVE_DEC_LOCK) += dec_and_lock.o
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@ -1,73 +0,0 @@
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/* mb.S: Out of line memory barriers.
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*
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* Copyright (C) 2005 David S. Miller (davem@davemloft.net)
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*/
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/* These are here in an effort to more fully work around
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* Spitfire Errata #51. Essentially, if a memory barrier
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* occurs soon after a mispredicted branch, the chip can stop
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* executing instructions until a trap occurs. Therefore, if
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* interrupts are disabled, the chip can hang forever.
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*
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* It used to be believed that the memory barrier had to be
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* right in the delay slot, but a case has been traced
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* recently wherein the memory barrier was one instruction
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* after the branch delay slot and the chip still hung. The
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* offending sequence was the following in sym_wakeup_done()
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* of the sym53c8xx_2 driver:
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*
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* call sym_ccb_from_dsa, 0
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* movge %icc, 0, %l0
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* brz,pn %o0, .LL1303
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* mov %o0, %l2
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* membar #LoadLoad
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*
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* The branch has to be mispredicted for the bug to occur.
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* Therefore, we put the memory barrier explicitly into a
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* "branch always, predicted taken" delay slot to avoid the
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* problem case.
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*/
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.text
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99: retl
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nop
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.globl mb
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mb: ba,pt %xcc, 99b
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membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad
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.size mb, .-mb
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.globl rmb
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rmb: ba,pt %xcc, 99b
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membar #LoadLoad
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.size rmb, .-rmb
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.globl wmb
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wmb: ba,pt %xcc, 99b
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membar #StoreStore
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.size wmb, .-wmb
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.globl membar_storeload
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membar_storeload:
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ba,pt %xcc, 99b
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membar #StoreLoad
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.size membar_storeload, .-membar_storeload
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.globl membar_storeload_storestore
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membar_storeload_storestore:
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ba,pt %xcc, 99b
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membar #StoreLoad | #StoreStore
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.size membar_storeload_storestore, .-membar_storeload_storestore
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.globl membar_storeload_loadload
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membar_storeload_loadload:
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ba,pt %xcc, 99b
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membar #StoreLoad | #LoadLoad
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.size membar_storeload_loadload, .-membar_storeload_loadload
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.globl membar_storestore_loadstore
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membar_storestore_loadstore:
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ba,pt %xcc, 99b
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membar #StoreStore | #LoadStore
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.size membar_storestore_loadstore, .-membar_storestore_loadstore
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@ -28,13 +28,48 @@ enum sparc_cpu {
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#define ARCH_SUN4C_SUN4 0
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#define ARCH_SUN4 0
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extern void mb(void);
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extern void rmb(void);
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extern void wmb(void);
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extern void membar_storeload(void);
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extern void membar_storeload_storestore(void);
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extern void membar_storeload_loadload(void);
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extern void membar_storestore_loadstore(void);
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/* These are here in an effort to more fully work around Spitfire Errata
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* #51. Essentially, if a memory barrier occurs soon after a mispredicted
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* branch, the chip can stop executing instructions until a trap occurs.
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* Therefore, if interrupts are disabled, the chip can hang forever.
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*
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* It used to be believed that the memory barrier had to be right in the
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* delay slot, but a case has been traced recently wherein the memory barrier
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* was one instruction after the branch delay slot and the chip still hung.
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* The offending sequence was the following in sym_wakeup_done() of the
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* sym53c8xx_2 driver:
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*
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* call sym_ccb_from_dsa, 0
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* movge %icc, 0, %l0
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* brz,pn %o0, .LL1303
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* mov %o0, %l2
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* membar #LoadLoad
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*
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* The branch has to be mispredicted for the bug to occur. Therefore, we put
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* the memory barrier explicitly into a "branch always, predicted taken"
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* delay slot to avoid the problem case.
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*/
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#define membar_safe(type) \
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do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
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" membar " type "\n" \
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"1:\n" \
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: : : "memory"); \
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} while (0)
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#define mb() \
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membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
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#define rmb() \
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membar_safe("#LoadLoad")
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#define wmb() \
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membar_safe("#StoreStore")
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#define membar_storeload() \
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membar_safe("#StoreLoad")
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#define membar_storeload_storestore() \
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membar_safe("#StoreLoad | #StoreStore")
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#define membar_storeload_loadload() \
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membar_safe("#StoreLoad | #LoadLoad")
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#define membar_storestore_loadstore() \
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membar_safe("#StoreStore | #LoadStore")
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#endif
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