drm/amdgpu: perform srbm soft reset always on SDMA resume
[ Upstream commit 253475c455
]
This can address the random SDMA hang after pci config reset
seen on Hawaii.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Sandeep Raghuraman <sandy.8925@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
5.4-rM2-2.2.x-imx-squashed
parent
7f6df0b085
commit
f449b902ba
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@ -1071,22 +1071,19 @@ static int cik_sdma_soft_reset(void *handle)
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{
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u32 srbm_soft_reset = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 tmp = RREG32(mmSRBM_STATUS2);
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u32 tmp;
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if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
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/* sdma0 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
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tmp |= SDMA0_F32_CNTL__HALT_MASK;
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WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
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}
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if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
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/* sdma1 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
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tmp |= SDMA0_F32_CNTL__HALT_MASK;
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WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
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}
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/* sdma0 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
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tmp |= SDMA0_F32_CNTL__HALT_MASK;
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WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
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/* sdma1 */
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tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
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tmp |= SDMA0_F32_CNTL__HALT_MASK;
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WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
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if (srbm_soft_reset) {
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tmp = RREG32(mmSRBM_SOFT_RESET);
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