drm/radeon/kms: display watermark fixes
- rs780/880 were using the wrong bandwidth functions - convert r1xx-r4xx to use the same pm sclk/mclk structs as r5xx+ - move bandwidth setup to a common function Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -437,7 +437,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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int evergreen_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 tmp;
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int chansize, numchan;
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@ -482,12 +481,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
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rdev->mc.real_vram_size = rdev->mc.aper_size;
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}
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r600_vram_gtt_location(rdev, &rdev->mc);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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@ -2025,6 +2025,7 @@ void r100_mc_init(struct radeon_device *rdev)
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radeon_vram_location(rdev, &rdev->mc, base);
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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@ -2416,11 +2417,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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/*
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* determine is there is enough bw for current mode
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*/
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mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
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temp_ff.full = rfixed_const(100);
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mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
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sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
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sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
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sclk_ff = rdev->pm.sclk;
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mclk_ff = rdev->pm.mclk;
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temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
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temp_ff.full = rfixed_const(temp);
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@ -482,6 +482,7 @@ void r300_mc_init(struct radeon_device *rdev)
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radeon_vram_location(rdev, &rdev->mc, base);
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
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@ -122,19 +122,13 @@ static void r520_vram_get_type(struct radeon_device *rdev)
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void r520_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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r520_vram_get_type(rdev);
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r100_vram_init_sizes(rdev);
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radeon_vram_location(rdev, &rdev->mc, 0);
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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radeon_update_bandwidth_info(rdev);
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}
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void r520_mc_program(struct radeon_device *rdev)
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@ -676,7 +676,6 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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int r600_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 tmp;
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int chansize, numchan;
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@ -720,14 +719,10 @@ int r600_mc_init(struct radeon_device *rdev)
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rdev->mc.real_vram_size = rdev->mc.aper_size;
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}
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r600_vram_gtt_location(rdev, &rdev->mc);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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if (rdev->flags & RADEON_IS_IGP)
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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@ -699,6 +699,7 @@ struct radeon_pm {
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fixed20_12 ht_bandwidth;
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fixed20_12 core_bandwidth;
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fixed20_12 sclk;
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fixed20_12 mclk;
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fixed20_12 needed_bandwidth;
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/* XXX: use a define for num power modes */
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struct radeon_power_state power_state[8];
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@ -1179,6 +1180,7 @@ extern void radeon_gart_restore(struct radeon_device *rdev);
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extern int radeon_modeset_init(struct radeon_device *rdev);
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extern void radeon_modeset_fini(struct radeon_device *rdev);
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extern bool radeon_card_posted(struct radeon_device *rdev);
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extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
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extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
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extern int radeon_clocks_init(struct radeon_device *rdev);
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extern void radeon_clocks_fini(struct radeon_device *rdev);
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@ -543,6 +543,43 @@ static struct radeon_asic r600_asic = {
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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};
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static struct radeon_asic rs780_asic = {
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.init = &r600_init,
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.fini = &r600_fini,
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.suspend = &r600_suspend,
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.resume = &r600_resume,
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.cp_commit = &r600_cp_commit,
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.vga_set_state = &r600_vga_set_state,
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.gpu_reset = &r600_gpu_reset,
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.gart_tlb_flush = &r600_pcie_gart_tlb_flush,
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.gart_set_page = &rs600_gart_set_page,
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.ring_test = &r600_ring_test,
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.ring_ib_execute = &r600_ring_ib_execute,
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.irq_set = &r600_irq_set,
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.irq_process = &r600_irq_process,
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.get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &r600_cs_parse,
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.copy_blit = &r600_copy_blit,
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.copy_dma = &r600_copy_blit,
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.copy = &r600_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = NULL,
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.set_memory_clock = NULL,
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.get_pcie_lanes = NULL,
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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.bandwidth_update = &rs690_bandwidth_update,
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.hpd_init = &r600_hpd_init,
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.hpd_fini = &r600_hpd_fini,
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.hpd_sense = &r600_hpd_sense,
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.hpd_set_polarity = &r600_hpd_set_polarity,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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};
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static struct radeon_asic rv770_asic = {
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.init = &rv770_init,
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.fini = &rv770_fini,
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@ -673,9 +710,11 @@ int radeon_asic_init(struct radeon_device *rdev)
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case CHIP_RV620:
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case CHIP_RV635:
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case CHIP_RV670:
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rdev->asic = &r600_asic;
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break;
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case CHIP_RS780:
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case CHIP_RS880:
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rdev->asic = &r600_asic;
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rdev->asic = &rs780_asic;
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break;
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case CHIP_RV770:
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case CHIP_RV730:
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@ -241,6 +241,36 @@ bool radeon_card_posted(struct radeon_device *rdev)
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}
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void radeon_update_bandwidth_info(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 sclk, mclk;
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if (rdev->flags & RADEON_IS_IGP) {
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sclk = radeon_get_engine_clock(rdev);
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mclk = rdev->clock.default_mclk;
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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rdev->pm.mclk.full = rfixed_const(mclk);
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rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
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a.full = rfixed_const(16);
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/* core_bandwidth = sclk(Mhz) * 16 */
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rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
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} else {
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sclk = radeon_get_engine_clock(rdev);
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mclk = radeon_get_memory_clock(rdev);
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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rdev->pm.mclk.full = rfixed_const(mclk);
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rdev->pm.mclk.full = rfixed_div(rdev->pm.mclk, a);
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}
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}
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bool radeon_boot_test_post_card(struct radeon_device *rdev)
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{
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if (radeon_card_posted(rdev))
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@ -475,8 +475,10 @@ void rs600_mc_init(struct radeon_device *rdev)
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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base = RREG32_MC(R_000004_MC_FB_LOCATION);
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base = G_000004_MC_FB_START(base) << 16;
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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radeon_vram_location(rdev, &rdev->mc, base);
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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void rs600_bandwidth_update(struct radeon_device *rdev)
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@ -132,7 +132,6 @@ void rs690_pm_info(struct radeon_device *rdev)
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void rs690_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u64 base;
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rs400_gart_adjust_size(rdev);
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@ -146,18 +145,10 @@ void rs690_mc_init(struct radeon_device *rdev)
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base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
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base = G_000100_MC_FB_START(base) << 16;
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rs690_pm_info(rdev);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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a.full = rfixed_const(16);
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/* core_bandwidth = sclk(Mhz) * 16 */
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rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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radeon_vram_location(rdev, &rdev->mc, base);
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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void rs690_line_buffer_adjust(struct radeon_device *rdev,
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@ -280,19 +280,13 @@ static void rv515_vram_get_type(struct radeon_device *rdev)
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void rv515_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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rv515_vram_get_type(rdev);
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r100_vram_init_sizes(rdev);
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radeon_vram_location(rdev, &rdev->mc, 0);
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if (!(rdev->flags & RADEON_IS_AGP))
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radeon_gtt_location(rdev, &rdev->mc);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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radeon_update_bandwidth_info(rdev);
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}
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uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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@ -868,7 +868,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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int rv770_mc_init(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 tmp;
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int chansize, numchan;
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@ -912,12 +911,8 @@ int rv770_mc_init(struct radeon_device *rdev)
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rdev->mc.real_vram_size = rdev->mc.aper_size;
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}
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r600_vram_gtt_location(rdev, &rdev->mc);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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