Merge branch 'parisc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes and cleanups from Helge Deller: "Nothing really important in this patchset: fix resource leaks in error paths, coding style cleanups and code removal" * 'parisc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Remove flush_user_dcache_range and flush_user_icache_range parisc: fix a printk parisc: ccio-dma: Handle return NULL error from ioremap_nocache parisc: Define access_ok() as macro parisc: eisa: Fix resource leaks in error paths parisc: eisa: Remove coding style errorshifive-unleashed-5.1
Linus Torvalds
commit
f47e2db43d
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@ -27,8 +27,6 @@ void flush_user_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_page_asm(void *);
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void flush_kernel_icache_page(void *);
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void flush_user_dcache_range(unsigned long, unsigned long);
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void flush_user_icache_range(unsigned long, unsigned long);
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/* Cache flush operations */
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@ -32,11 +32,7 @@
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* that put_user is the same as __put_user, etc.
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*/
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static inline long access_ok(int type, const void __user * addr,
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unsigned long size)
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{
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return 1;
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}
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#define access_ok(type, uaddr, size) (1)
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#define put_user __put_user
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#define get_user __get_user
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@ -574,24 +574,6 @@ void flush_cache_mm(struct mm_struct *mm)
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}
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}
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void
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flush_user_dcache_range(unsigned long start, unsigned long end)
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{
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if ((end - start) < parisc_cache_flush_threshold)
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flush_user_dcache_range_asm(start,end);
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else
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flush_data_cache();
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}
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void
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flush_user_icache_range(unsigned long start, unsigned long end)
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{
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if ((end - start) < parisc_cache_flush_threshold)
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flush_user_icache_range_asm(start,end);
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else
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flush_instruction_cache();
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}
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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@ -233,6 +233,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
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struct rt_sigframe __user *frame;
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unsigned long rp, usp;
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unsigned long haddr, sigframe_size;
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unsigned long start, end;
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int err = 0;
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#ifdef CONFIG_64BIT
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struct compat_rt_sigframe __user * compat_frame;
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@ -300,10 +301,10 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
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}
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#endif
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flush_user_dcache_range((unsigned long) &frame->tramp[0],
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(unsigned long) &frame->tramp[TRAMP_SIZE]);
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flush_user_icache_range((unsigned long) &frame->tramp[0],
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(unsigned long) &frame->tramp[TRAMP_SIZE]);
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start = (unsigned long) &frame->tramp[0];
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end = (unsigned long) &frame->tramp[TRAMP_SIZE];
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flush_user_dcache_range_asm(start, end);
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flush_user_icache_range_asm(start, end);
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/* TRAMP Words 0-4, Length 5 = SIGRESTARTBLOCK_TRAMP
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* TRAMP Words 5-9, Length 4 = SIGRETURN_TRAMP
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@ -549,8 +550,8 @@ insert_restart_trampoline(struct pt_regs *regs)
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WARN_ON(err);
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/* flush data/instruction cache for new insns */
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flush_user_dcache_range(start, end);
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flush_user_icache_range(start, end);
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flush_user_dcache_range_asm(start, end);
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flush_user_icache_range_asm(start, end);
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regs->gr[31] = regs->gr[30] + 8;
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return;
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@ -239,8 +239,8 @@ show_signal_msg(struct pt_regs *regs, unsigned long code,
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vma ? ',':'\n');
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if (vma)
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pr_warn(KERN_CONT " vm_start = 0x%08lx, vm_end = 0x%08lx\n",
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vma->vm_start, vma->vm_end);
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pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
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vma->vm_start, vma->vm_end);
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show_regs(regs);
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}
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@ -1539,7 +1539,7 @@ static int __init ccio_probe(struct parisc_device *dev)
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ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
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if (ioc == NULL) {
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printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
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return 1;
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return -ENOMEM;
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}
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ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
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@ -1554,6 +1554,10 @@ static int __init ccio_probe(struct parisc_device *dev)
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ioc->hw_path = dev->hw_path;
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ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096);
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if (!ioc->ioc_regs) {
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kfree(ioc);
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return -ENOMEM;
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}
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ccio_ioc_init(ioc);
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ccio_init_resources(ioc);
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hppa_dma_ops = &ccio_ops;
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@ -14,16 +14,16 @@
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* Wax ASIC also includes a PS/2 and RS-232 controller, but those are
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* dealt with elsewhere; this file is concerned only with the EISA portions
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* of Wax.
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*
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*
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*
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*
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* HINT:
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* -----
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* To allow an ISA card to work properly in the EISA slot you need to
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* set an edge trigger level. This may be done on the palo command line
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* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
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* set an edge trigger level. This may be done on the palo command line
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* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
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* n and n2 as the irq levels you want to use.
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*
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* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
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*
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* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
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* irq levels 10 and 11.
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*/
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@ -46,9 +46,9 @@
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#include <asm/eisa_eeprom.h>
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#if 0
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#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
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#define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
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#else
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#define EISA_DBG(msg, arg... )
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#define EISA_DBG(msg, arg...)
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#endif
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#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
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@ -108,7 +108,7 @@ void eisa_out8(unsigned char data, unsigned short port)
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void eisa_out16(unsigned short data, unsigned short port)
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{
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if (EISA_bus)
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if (EISA_bus)
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gsc_writew(cpu_to_le16(data), eisa_permute(port));
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}
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@ -135,9 +135,9 @@ static int master_mask;
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static int slave_mask;
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/* the trig level can be set with the
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* eisa_irq_edge=n,n,n commandline parameter
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* We should really read this from the EEPROM
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* in the furure.
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* eisa_irq_edge=n,n,n commandline parameter
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* We should really read this from the EEPROM
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* in the furure.
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*/
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/* irq 13,8,2,1,0 must be edge */
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static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
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@ -170,7 +170,7 @@ static void eisa_unmask_irq(struct irq_data *d)
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unsigned int irq = d->irq;
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unsigned long flags;
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EISA_DBG("enable irq %d\n", irq);
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spin_lock_irqsave(&eisa_irq_lock, flags);
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if (irq & 8) {
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slave_mask &= ~(1 << (irq&7));
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@ -194,7 +194,7 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
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{
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int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
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unsigned long flags;
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spin_lock_irqsave(&eisa_irq_lock, flags);
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/* read IRR command */
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eisa_out8(0x0a, 0x20);
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@ -202,31 +202,31 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
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EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
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irq, eisa_in8(0x20), eisa_in8(0xa0));
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/* read ISR command */
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eisa_out8(0x0a, 0x20);
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eisa_out8(0x0a, 0xa0);
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EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
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eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
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irq &= 0xf;
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/* mask irq and write eoi */
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if (irq & 8) {
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slave_mask |= (1 << (irq&7));
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eisa_out8(slave_mask, 0xa1);
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eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
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eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
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eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */
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} else {
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master_mask |= (1 << (irq&7));
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eisa_out8(master_mask, 0x21);
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eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
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eisa_out8(0x60|irq, 0x20); /* 'Specific EOI' to master */
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}
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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generic_handle_irq(irq);
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spin_lock_irqsave(&eisa_irq_lock, flags);
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/* unmask */
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if (irq & 8) {
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@ -254,44 +254,44 @@ static struct irqaction irq2_action = {
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static void init_eisa_pic(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&eisa_irq_lock, flags);
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eisa_out8(0xff, 0x21); /* mask during init */
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eisa_out8(0xff, 0xa1); /* mask during init */
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/* master pic */
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eisa_out8(0x11,0x20); /* ICW1 */
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eisa_out8(0x00,0x21); /* ICW2 */
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eisa_out8(0x04,0x21); /* ICW3 */
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eisa_out8(0x01,0x21); /* ICW4 */
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eisa_out8(0x40,0x20); /* OCW2 */
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eisa_out8(0x11, 0x20); /* ICW1 */
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eisa_out8(0x00, 0x21); /* ICW2 */
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eisa_out8(0x04, 0x21); /* ICW3 */
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eisa_out8(0x01, 0x21); /* ICW4 */
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eisa_out8(0x40, 0x20); /* OCW2 */
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/* slave pic */
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eisa_out8(0x11,0xa0); /* ICW1 */
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eisa_out8(0x08,0xa1); /* ICW2 */
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eisa_out8(0x02,0xa1); /* ICW3 */
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eisa_out8(0x01,0xa1); /* ICW4 */
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eisa_out8(0x40,0xa0); /* OCW2 */
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eisa_out8(0x11, 0xa0); /* ICW1 */
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eisa_out8(0x08, 0xa1); /* ICW2 */
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eisa_out8(0x02, 0xa1); /* ICW3 */
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eisa_out8(0x01, 0xa1); /* ICW4 */
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eisa_out8(0x40, 0xa0); /* OCW2 */
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udelay(100);
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slave_mask = 0xff;
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master_mask = 0xfb;
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slave_mask = 0xff;
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master_mask = 0xfb;
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eisa_out8(slave_mask, 0xa1); /* OCW1 */
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eisa_out8(master_mask, 0x21); /* OCW1 */
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/* setup trig level */
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EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
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eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
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eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
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eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
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EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
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EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
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EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
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EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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}
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@ -305,7 +305,7 @@ static int __init eisa_probe(struct parisc_device *dev)
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char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
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printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
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printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
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name, (unsigned long)dev->hpa.start);
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eisa_dev.hba.dev = dev;
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@ -334,16 +334,16 @@ static int __init eisa_probe(struct parisc_device *dev)
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result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
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if (result) {
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printk(KERN_ERR "EISA: request_irq failed!\n");
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return result;
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goto error_release;
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}
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/* Reserve IRQ2 */
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setup_irq(2, &irq2_action);
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for (i = 0; i < 16; i++) {
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irq_set_chip_and_handler(i, &eisa_interrupt_type,
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handle_simple_irq);
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}
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EISA_bus = 1;
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if (dev->num_addrs) {
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@ -358,6 +358,11 @@ static int __init eisa_probe(struct parisc_device *dev)
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}
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}
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eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
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if (!eisa_eeprom_addr) {
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result = -ENOMEM;
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printk(KERN_ERR "EISA: ioremap_nocache failed!\n");
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goto error_free_irq;
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}
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result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
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&eisa_dev.hba.lmmio_space);
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init_eisa_pic();
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@ -372,11 +377,20 @@ static int __init eisa_probe(struct parisc_device *dev)
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eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
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if (eisa_root_register (&eisa_dev.root)) {
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printk(KERN_ERR "EISA: Failed to register EISA root\n");
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return -1;
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result = -ENOMEM;
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goto error_iounmap;
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}
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}
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|
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|
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return 0;
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|
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error_iounmap:
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iounmap(eisa_eeprom_addr);
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error_free_irq:
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free_irq(dev->irq, &eisa_dev);
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error_release:
|
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release_resource(&eisa_dev.hba.io_space);
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return result;
|
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}
|
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|
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static const struct parisc_device_id eisa_tbl[] = {
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|
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@ -404,7 +418,7 @@ void eisa_make_irq_level(int num)
|
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{
|
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if (eisa_irq_configured& (1<<num)) {
|
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printk(KERN_WARNING
|
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"IRQ %d polarity configured twice (last to level)\n",
|
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"IRQ %d polarity configured twice (last to level)\n",
|
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num);
|
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}
|
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eisa_irq_level |= (1<<num); /* set the corresponding bit */
|
||||
|
|
@ -414,7 +428,7 @@ void eisa_make_irq_level(int num)
|
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void eisa_make_irq_edge(int num)
|
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{
|
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if (eisa_irq_configured& (1<<num)) {
|
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printk(KERN_WARNING
|
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printk(KERN_WARNING
|
||||
"IRQ %d polarity configured twice (last to edge)\n",
|
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num);
|
||||
}
|
||||
|
|
@ -430,18 +444,18 @@ static int __init eisa_irq_setup(char *str)
|
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EISA_DBG("IRQ setup\n");
|
||||
while (cur != NULL) {
|
||||
char *pe;
|
||||
|
||||
|
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val = (int) simple_strtoul(cur, &pe, 0);
|
||||
if (val > 15 || val < 0) {
|
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printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
|
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continue;
|
||||
}
|
||||
if (val == 2) {
|
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if (val == 2) {
|
||||
val = 9;
|
||||
}
|
||||
eisa_make_irq_edge(val); /* clear the corresponding bit */
|
||||
EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
|
||||
|
||||
|
||||
if ((cur = strchr(cur, ','))) {
|
||||
cur++;
|
||||
} else {
|
||||
|
|
|
|||
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