media: dt-bindings: add bindings for i.MX8QXP parallel interface
Add bindings documentation for i.MX8QXP parallel interface device Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>5.4-rM2-2.2.x-imx-squashed
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Freescale i.MX8QXP Parallel Capture Interface
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=========================
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parallel interface node
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--------------
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This is the device node for the parallel capture interface in i.MX8QXP SoC.
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Required properties:
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- compatible : "fsl,mxc-parallel-csi";
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- reg : base address and length of the register set for the device;
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- clocks : list of clock specifiers
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- clock-names : must contain "pixel", "ipg", "div" and "dpll" entries,
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matching entries in the clock property;
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- assigned-clocks : need to set the parent of pixel clock;
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- assigned-clock-parent: set the pll as the parent of pixel clock;
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- assigned-clock-rates : the value should be 160MHz;
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- power-domains : a phandle to the power domain, see
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- power-domain-name : must contain "pd_pi", "pd_isi_ch0".
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port node
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- reg : can take the values 0 which mean the port is a sink port
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example:
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parallel_csi: pcsi@58261000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mxc-parallel-csi";
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reg = <0x58261000 0x1000>;
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clocks = <&pi_lpcg IMX_PI_LPCG_PI0_PIXEL_CLK>,
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<&pi_lpcg IMX_PI_LPCG_PI0_IPG_CLK>,
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<&clk IMX_PARALLEL_PER_DIV_CLK>,
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<&clk IMX_PARALLEL_DPLL_CLK>;
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clock-names = "pixel", "ipg", "div", "dpll";
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assigned-clocks = <&clk IMX_PARALLEL_PER_DIV_CLK>;
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assigned-clock-parents = <&clk IMX_PARALLEL_DPLL_CLK>;
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assigned-clock-rates = <160000000>; /* 160MHz */
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power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>;
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power-domain-names = "pd_pi", "pd_isi_ch0";
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port@0 {
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reg = <0>;
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parallel_csi_ep: endpoint {
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remote-endpoint = <&ov5640_ep>;
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};
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};
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};
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