arm: dts: mt7623: add support for Bananapi R2 (BPI-R2) board
Add support for the Bananapi R2 (BPI-R2) development board from BIPAI KEJI. Detailed hardware information for BPI-R2 which could be found on http://www.banana-pi.org/r2.html The patch added nodes into the SoC-level file mt7623.dtsi such as CPU OPP table and thermal zone treating CPU as one of cooling devices and also added nodes into board-level file mt7623n-bananapi-bpi-r2.dts such as MediaTek GMAC, MT7530 Switch, the crypto engine, USB, IR, I2S, I2C, UART, SPI, PWM, GPIO keys, GPIO LEDs and PMIC LEDs. As to the other missing hardware and peripherals, they would be added and integrated continuously. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>hifive-unleashed-5.1
Sean Wang
Matthias Brugger
parent
876680cf23
commit
f4ff257cd1
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@ -49,6 +49,8 @@ Supported boards:
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- Reference board for MT7623n with NAND:
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Required root node properties:
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- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
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- Bananapi BPI-R2 board:
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- compatible = "bananapi,bpi-r2", "mediatek,mt7623";
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- MTK mt8127 tablet moose EVB:
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Required root node properties:
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- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
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@ -1050,6 +1050,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt6589-aquaris5.dtb \
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mt6592-evb.dtb \
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mt7623n-rfb-nand.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
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@ -21,12 +21,58 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "skeleton64.dtsi"
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/ {
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compatible = "mediatek,mt7623";
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interrupt-parent = <&sysirq>;
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-98000000 {
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opp-hz = /bits/ 64 <98000000>;
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opp-microvolt = <1050000>;
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};
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opp-198000000 {
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opp-hz = /bits/ 64 <198000000>;
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opp-microvolt = <1050000>;
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};
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opp-398000000 {
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opp-hz = /bits/ 64 <398000000>;
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opp-microvolt = <1050000>;
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};
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opp-598000000 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1050000>;
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};
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opp-747500000 {
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opp-hz = /bits/ 64 <747500000>;
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opp-microvolt = <1050000>;
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};
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opp-1040000000 {
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opp-hz = /bits/ 64 <1040000000>;
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opp-microvolt = <1150000>;
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};
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opp-1196000000 {
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opp-hz = /bits/ 64 <1196000000>;
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opp-microvolt = <1200000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1300000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -36,21 +82,31 @@
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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};
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@ -74,6 +130,56 @@
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clock-output-names = "clk26m";
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};
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thermal-zones {
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cpu_thermal: cpu_thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal 0>;
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trips {
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cpu_passive: cpu_passive {
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temperature = <47000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_active: cpu_active {
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temperature = <67000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_hot: cpu_hot {
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temperature = <87000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu_crit {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_passive>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_active>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map2 {
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trip = <&cpu_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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@ -172,7 +278,7 @@
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clock-names = "spi", "wrap";
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};
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cir: cir@0x10013000 {
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cir: cir@10013000 {
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compatible = "mediatek,mt7623-cir";
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reg = <0 0x10013000 0 0x1000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
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@ -193,7 +299,7 @@
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,mt8173-efuse";
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reg = <0 0x10206000 0 0x1000>;
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reg = <0 0x10206000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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thermal_calibration_data: calib@424 {
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@ -561,7 +667,8 @@
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};
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u3phy1: usb-phy@1a1c4000 {
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compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
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compatible = "mediatek,mt7623-u3phy",
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"mediatek,mt2701-u3phy";
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reg = <0 0x1a1c4000 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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@ -599,7 +706,8 @@
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};
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u3phy2: usb-phy@1a244000 {
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compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";
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compatible = "mediatek,mt7623-u3phy",
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"mediatek,mt2701-u3phy";
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reg = <0 0x1a244000 0 0x0700>;
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clocks = <&clk26m>;
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clock-names = "u3phya_ref";
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@ -639,7 +747,9 @@
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt2701-eth", "syscon";
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compatible = "mediatek,mt7623-eth",
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"mediatek,mt2701-eth",
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"syscon";
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reg = <0 0x1b100000 0 0x20000>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
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@ -0,0 +1,443 @@
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/*
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* Copyright 2017 Sean Wang <sean.wang@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7623.dtsi"
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#include "mt6323.dtsi"
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/ {
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model = "Bananapi BPI-R2";
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compatible = "bananapi,bpi-r2", "mediatek,mt7623";
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aliases {
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serial2 = &uart2;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6323_vproc_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6323_vproc_reg>;
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};
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cpu@2 {
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proc-supply = <&mt6323_vproc_reg>;
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};
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cpu@3 {
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proc-supply = <&mt6323_vproc_reg>;
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&key_pins_a>;
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factory {
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label = "factory";
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linux,code = <BTN_0>;
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gpios = <&pio 256 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_pins_a>;
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red {
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label = "bpi-r2:pio:red";
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gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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green {
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label = "bpi-r2:pio:green";
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gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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blue {
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label = "bpi-r2:pio:blue";
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gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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memory@80000000 {
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reg = <0 0x80000000 0 0x40000000>;
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};
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&cir_pins_a>;
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status = "okay";
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "mediatek,mt7530";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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pinctrl-names = "default";
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reset-gpios = <&pio 33 0>;
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core-supply = <&mt6323_vpa_reg>;
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io-supply = <&mt6323_vemc3v3_reg>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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label = "wan";
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};
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port@1 {
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reg = <1>;
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label = "lan0";
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};
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port@2 {
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reg = <2>;
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label = "lan1";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan3";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins_a>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins_a>;
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status = "okay";
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};
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&pio {
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cir_pins_a:cir@0 {
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pins_cir {
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pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
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bias-disable;
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};
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};
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i2c0_pins_a: i2c@0 {
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pins_i2c0 {
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pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
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<MT7623_PIN_76_SCL0_FUNC_SCL0>;
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bias-disable;
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};
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};
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i2c1_pins_a: i2c@1 {
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pin_i2c1 {
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pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
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<MT7623_PIN_58_SCL1_FUNC_SCL1>;
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bias-disable;
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};
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};
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i2s0_pins_a: i2s@0 {
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pin_i2s0 {
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pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
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<MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
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<MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
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<MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
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<MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
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drive-strength = <MTK_DRIVE_12mA>;
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bias-pull-down;
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};
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};
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i2s1_pins_a: i2s@1 {
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pin_i2s1 {
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pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
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<MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
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<MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
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<MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
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<MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
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drive-strength = <MTK_DRIVE_12mA>;
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bias-pull-down;
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};
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};
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key_pins_a: keys@0 {
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pins_keys {
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pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
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<MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
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input-enable;
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};
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};
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led_pins_a: leds@0 {
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pins_leds {
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pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
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<MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
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<MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
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};
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};
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mmc0_pins_default: mmc0default {
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pins_cmd_dat {
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pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
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<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
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<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
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<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
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<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
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<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
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<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
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<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
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<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pins_rst {
|
||||
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_uhs: mmc0 {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
|
||||
<MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
|
||||
<MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
|
||||
<MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
|
||||
<MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
|
||||
<MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
|
||||
<MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
|
||||
<MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
|
||||
<MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_2mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
|
||||
drive-strength = <MTK_DRIVE_2mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
|
||||
pins_rst {
|
||||
pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_pins_default: mmc1default {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
|
||||
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
|
||||
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
|
||||
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
|
||||
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
|
||||
bias-pull-down;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc1_pins_uhs: mmc1 {
|
||||
pins_cmd_dat {
|
||||
pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
|
||||
<MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
|
||||
<MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
|
||||
<MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
|
||||
<MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
|
||||
pins_clk {
|
||||
pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0_pins_a: spi@0 {
|
||||
pins_spi {
|
||||
pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
|
||||
<MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
|
||||
<MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
|
||||
<MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_pins_a: pwm@0 {
|
||||
pins_pwm {
|
||||
pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
|
||||
<MT7623_PIN_204_PWM1_FUNC_PWM1>,
|
||||
<MT7623_PIN_205_PWM2_FUNC_PWM2>,
|
||||
<MT7623_PIN_206_PWM3_FUNC_PWM3>,
|
||||
<MT7623_PIN_207_PWM4_FUNC_PWM4>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins_a: uart@0 {
|
||||
pins_dat {
|
||||
pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
|
||||
<MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins_a: uart@1 {
|
||||
pins_dat {
|
||||
pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
|
||||
<MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwrap {
|
||||
mt6323 {
|
||||
mt6323led: led {
|
||||
compatible = "mediatek,mt6323-led";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
label = "bpi-r2:isink:green";
|
||||
default-state = "off";
|
||||
};
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
label = "bpi-r2:isink:red";
|
||||
default-state = "off";
|
||||
};
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
label = "bpi-r2:isink:blue";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&u3phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u3phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
vusb33-supply = <&mt6323_vusb_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
vusb33-supply = <&mt6323_vusb_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue