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pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base

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The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not worked around when
developing the driver, which makes IRQ not working.

Fix the IRQ bank base.

Fixes: 56d9e4a760 ("pinctrl: sunxi: add driver for V3s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Icenowy Zheng 2017-08-01 22:54:16 +08:00 committed by Linus Walleij
parent 3f713b7c22
commit f547b3de90
1 changed files with 1 additions and 0 deletions
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drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
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@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
.pins = sun8i_v3s_pins,
.npins = ARRAY_SIZE(sun8i_v3s_pins),
.irq_banks = 2,
.irq_bank_base = 1,
.irq_read_needs_mux = true
};