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ASoC: mxs-saif: Fix channel swap for 24-bit format 

Playing 24-bit format file leads to channel swap on mx28 and the reason is that
the current driver performs one write/read to/from the SAIF_DATA register to
trigger the transfer.

This approach works fine for S16_LE case because SAIF_DATA is a 32-bit register
and thus is capable of storing the 16-bit left and right channels, but for the
S24_LE case it can only store one channel, so in order to not lose the FIFO sync
an extra read/write is needed.

Reported-by: Dan Winner <DWinner@tc-helicon.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Dan Winner <DWinner@tc-helicon.com>
Acked-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
hifive-unleashed-5.1
Fabio Estevam 2012-11-01 15:57:11 -02:00 committed by Mark Brown
parent 9f4c3f1cde
commit f55f14752e
1 changed files with 12 additions and 4 deletions
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16
sound/soc/mxs/mxs-saif.c
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@ -523,16 +523,24 @@ static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
/*
* write a data to saif data register to trigger
* the transfer
* write data to saif data register to trigger
* the transfer.
* For 24-bit format the 32-bit FIFO register stores
* only one channel, so we need to write twice.
* This is also safe for the other non 24-bit formats.
*/
__raw_writel(0, saif->base + SAIF_DATA);
__raw_writel(0, saif->base + SAIF_DATA);
} else {
/*
* read a data from saif data register to trigger
* the receive
* read data from saif data register to trigger
* the receive.
* For 24-bit format the 32-bit FIFO register stores
* only one channel, so we need to read twice.
* This is also safe for the other non 24-bit formats.
*/
__raw_readl(saif->base + SAIF_DATA);
__raw_readl(saif->base + SAIF_DATA);
}
master_saif->ongoing = 1;