Fixes for timer, sram, memory corruption, and one board
file that affect booting on various omaps. Then some PM related fixes for reset, sleep and wakeup. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQSRZ+AAoJEBvUPslcq6VzEicQAI2LzTL+kKlYjiXHXJJjkFPJ +3NJDw36thl4W9wA/tRyesqj8CDmpNRIZxoUtxeZqbDzn19erCiuEqLrmP9eAJdX eYmuDwGaoM6yOom8LswbfvXlDCVlkK4BtYLXMbhkgcNWXMbpk52f357RHPh3bN3I 6Na2YwayB6cjmwRGXeWVEk+fDxPT+GbY3fsUZPg7BNZ14HdzEI+DOzfGJSO3cQPR NY5FpLSmLMkCkulyuuuMSznLuLRxjHsRgBwtPSJltsytJAcFwWnXLY5DqtQXCoZw vnltYP1QuUHXSTbXYGiU1nDd1ZBz3Z36g90/Xu3WeMUSh7rRzI38XUN3ouhbz3CP hKYWLl1LtDilKdYVZTeZRL7afwBbueNYf0HRLqscM1ZO7Iv4dTiOcCOivOp5K6K0 OYX8Ac/Xyrd0J4Z9DVGkyMmGeLt6hOiEXr+rvm/3eKGZ2KuNenm0kyxhncYU810T O0ygecCkU0LGmJEBUEac3pRP7uNlmEFgvB/B62tfaoTAdwUcWw8v044pAkhJyI+k 4KPP74Timohr0Bgqh0zhNi/ts3Ya9kFF7gPVK1aS+L6YHYy+oCmUcVVj5na/rvFo 9KgunUtTX2ljAgMp7oRevFtlF6izhNDMYvY+iHjkERDQf5isksOw9WhWacgnhvrm cHV8QVMc6XLxo7Krk+4M =fUO5 -----END PGP SIGNATURE----- Merge tag 'omap-fixes-for-v3.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Fixes for timer, sram, memory corruption, and one board file that affect booting on various omaps. Then some PM related fixes for reset, sleep and wakeup. * tag 'omap-fixes-for-v3.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4: Fix array size for irq_target_cpu ARM: OMAP4: hwmod data: temporarily comment out data for the sl2if IP block ARM: OMAP: hwmod code: Disable module when hwmod enable fails ARM: OMAP3: hwmod data: fix iva2 reset info ARM: OMAP3xxx: clockdomain: fix software supervised wakeup/sleep ARM: OMAP2+: am33xx: Fix the timer fck clock naming convention ARM: OMAP: Config fix for omap3-touchbook board ARM: OMAP: sram: skip the first 16K on OMAP3 HS ARM: OMAP: sram: fix OMAP4 errata handling ARM: OMAP: timer: obey the !CONFIG_OMAP_32K_TIMER
This commit is contained in:
commit
f5a60d4efc
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@ -232,10 +232,11 @@ config MACH_OMAP3_PANDORA
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select OMAP_PACKAGE_CBB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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config MACH_OMAP3_TOUCHBOOK
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config MACH_TOUCHBOOK
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bool "OMAP3 Touch Book"
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depends on ARCH_OMAP3
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default y
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select OMAP_PACKAGE_CBB
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config MACH_OMAP_3430SDP
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bool "OMAP 3430 SDP board"
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@ -255,7 +255,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o
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obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
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obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
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obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
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obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o
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obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
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obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
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obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o
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@ -1036,13 +1036,13 @@ static struct omap_clk am33xx_clks[] = {
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CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
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CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
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CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
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CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
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CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
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CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
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CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
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CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
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CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
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CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
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CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
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CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
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CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
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CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
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CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
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CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
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CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
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CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
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CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
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CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
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@ -241,6 +241,52 @@ static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
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_clkdm_del_autodeps(clkdm);
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}
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static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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_disable_hwsup(clkdm);
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_clkdm_add_autodeps(clkdm);
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_enable_hwsup(clkdm);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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omap3_clkdm_wakeup(clkdm);
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}
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return 0;
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}
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static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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_disable_hwsup(clkdm);
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_clkdm_del_autodeps(clkdm);
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_enable_hwsup(clkdm);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
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omap3_clkdm_sleep(clkdm);
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}
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return 0;
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}
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struct clkdm_ops omap2_clkdm_operations = {
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.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
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.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
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@ -267,6 +313,6 @@ struct clkdm_ops omap3_clkdm_operations = {
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.clkdm_wakeup = omap3_clkdm_wakeup,
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.clkdm_allow_idle = omap3_clkdm_allow_idle,
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.clkdm_deny_idle = omap3_clkdm_deny_idle,
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.clkdm_clk_enable = omap2_clkdm_clk_enable,
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.clkdm_clk_disable = omap2_clkdm_clk_disable,
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.clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
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.clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
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};
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@ -67,6 +67,7 @@
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#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
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/* CM_IDLEST_IVA2 */
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#define OMAP3430_ST_IVA2_SHIFT 0
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#define OMAP3430_ST_IVA2_MASK (1 << 0)
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/* CM_IDLEST_PLL_IVA2 */
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@ -46,7 +46,7 @@
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static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[NR_IRQS];
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static unsigned int irq_target_cpu[MAX_IRQS];
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static unsigned int irq_banks = MAX_NR_REG_BANKS;
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static unsigned int max_irqs = MAX_IRQS;
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static unsigned int omap_secure_apis;
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@ -1889,6 +1889,7 @@ static int _enable(struct omap_hwmod *oh)
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_enable_sysc(oh);
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}
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} else {
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_omap4_disable_module(oh);
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_disable_clocks(oh);
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pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
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oh->name, r);
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@ -100,9 +100,9 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
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/* IVA2 (IVA2) */
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static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
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{ .name = "logic", .rst_shift = 0 },
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{ .name = "seq0", .rst_shift = 1 },
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{ .name = "seq1", .rst_shift = 2 },
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{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
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{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
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{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
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};
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static struct omap_hwmod omap3xxx_iva_hwmod = {
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@ -112,6 +112,15 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
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.rst_lines = omap3xxx_iva_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
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.main_clk = "iva2_ck",
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.prcm = {
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.omap2 = {
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.module_offs = OMAP3430_IVA2_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
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}
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},
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};
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/* timer class */
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@ -4210,7 +4210,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
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};
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/* dsp -> sl2if */
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static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
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static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
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.master = &omap44xx_dsp_hwmod,
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.slave = &omap44xx_sl2if_hwmod,
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.clk = "dpll_iva_m5x2_ck",
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@ -4828,7 +4828,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
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};
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/* iva -> sl2if */
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static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
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static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
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.master = &omap44xx_iva_hwmod,
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.slave = &omap44xx_sl2if_hwmod,
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.clk = "dpll_iva_m5x2_ck",
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@ -5362,7 +5362,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
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};
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/* l3_main_2 -> sl2if */
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static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
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static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
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.master = &omap44xx_l3_main_2_hwmod,
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.slave = &omap44xx_sl2if_hwmod,
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.clk = "l3_div_ck",
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@ -6032,7 +6032,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_abe__dmic,
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&omap44xx_l4_abe__dmic_dma,
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&omap44xx_dsp__iva,
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&omap44xx_dsp__sl2if,
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/* &omap44xx_dsp__sl2if, */
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&omap44xx_l4_cfg__dsp,
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&omap44xx_l3_main_2__dss,
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&omap44xx_l4_per__dss,
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@ -6068,7 +6068,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_per__i2c4,
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&omap44xx_l3_main_2__ipu,
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&omap44xx_l3_main_2__iss,
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&omap44xx_iva__sl2if,
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/* &omap44xx_iva__sl2if, */
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&omap44xx_l3_main_2__iva,
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&omap44xx_l4_wkup__kbd,
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&omap44xx_l4_cfg__mailbox,
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@ -6099,7 +6099,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
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&omap44xx_l4_cfg__cm_core,
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&omap44xx_l4_wkup__prm,
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&omap44xx_l4_wkup__scrm,
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&omap44xx_l3_main_2__sl2if,
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/* &omap44xx_l3_main_2__sl2if, */
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&omap44xx_l4_abe__slimbus1,
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&omap44xx_l4_abe__slimbus1_dma,
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&omap44xx_l4_per__slimbus2,
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@ -260,6 +260,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
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return 0;
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}
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#ifdef CONFIG_OMAP_32K_TIMER
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/* Setup free-running counter for clocksource */
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static int __init omap2_sync32k_clocksource_init(void)
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{
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return ret;
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}
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#else
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static inline int omap2_sync32k_clocksource_init(void)
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{
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return -ENODEV;
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}
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#endif
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static void __init omap2_gptimer_clocksource_init(int gptimer_id,
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const char *fck_source)
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@ -68,6 +68,7 @@
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static unsigned long omap_sram_start;
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static void __iomem *omap_sram_base;
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static unsigned long omap_sram_skip;
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static unsigned long omap_sram_size;
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static void __iomem *omap_sram_ceil;
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@ -106,6 +107,7 @@ static int is_sram_locked(void)
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*/
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static void __init omap_detect_sram(void)
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{
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omap_sram_skip = SRAM_BOOTLOADER_SZ;
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if (cpu_class_is_omap2()) {
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if (is_sram_locked()) {
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if (cpu_is_omap34xx()) {
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@ -113,6 +115,7 @@ static void __init omap_detect_sram(void)
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if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
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(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
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omap_sram_size = 0x7000; /* 28K */
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omap_sram_skip += SZ_16K;
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} else {
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omap_sram_size = 0x8000; /* 32K */
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}
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@ -175,8 +178,10 @@ static void __init omap_map_sram(void)
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return;
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#ifdef CONFIG_OMAP4_ERRATA_I688
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if (cpu_is_omap44xx()) {
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omap_sram_start += PAGE_SIZE;
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omap_sram_size -= SZ_16K;
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}
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#endif
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if (cpu_is_omap34xx()) {
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/*
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@ -203,8 +208,8 @@ static void __init omap_map_sram(void)
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* Looks like we need to preserve some bootloader code at the
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* beginning of SRAM for jumping to flash for reboot to work...
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*/
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memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
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omap_sram_size - SRAM_BOOTLOADER_SZ);
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memset_io(omap_sram_base + omap_sram_skip, 0,
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omap_sram_size - omap_sram_skip);
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}
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/*
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@ -218,7 +223,7 @@ void *omap_sram_push_address(unsigned long size)
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{
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unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
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available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
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available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
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if (size > available) {
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pr_err("Not enough space in SRAM\n");
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