OMAPDSS: HDMI: Add OMAP5 HDMI support
This adds a new driver to omapdss for OMAP5 HDMI. However, the new driver uses common HDMI files which are shared with OMAP4 HDMI driver. OMAP5 HDMI has a different HDMI core IP compared to OMAP4, but has very similar PLL and PHY IPs which can be handled with common code. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>hifive-unleashed-5.1
Tomi Valkeinen
parent
2d64b1b314
commit
f5bab22291
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@ -72,6 +72,19 @@ config OMAP4_DSS_HDMI
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config OMAP4_DSS_HDMI_AUDIO
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bool
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config OMAP5_DSS_HDMI
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bool "HDMI support for OMAP5"
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default n
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select OMAP2_DSS_HDMI_COMMON
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help
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HDMI Interface for OMAP5 and similar cores. This adds the High
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Definition Multimedia Interface. See http://www.hdmi.org/ for HDMI
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specification.
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config OMAP5_DSS_HDMI_AUDIO
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depends on OMAP5_DSS_HDMI
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bool
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config OMAP2_DSS_SDI
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bool "SDI support"
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default n
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@ -13,4 +13,5 @@ omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o
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omapdss-$(CONFIG_OMAP2_DSS_HDMI_COMMON) += hdmi_common.o hdmi_wp.o hdmi_pll.o \
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hdmi_phy.o
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omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi4.o hdmi4_core.o
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omapdss-$(CONFIG_OMAP5_DSS_HDMI) += hdmi5.o hdmi5_core.o
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ccflags-$(CONFIG_OMAP2_DSS_DEBUG) += -DDEBUG
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@ -268,6 +268,9 @@ static int (*dss_output_drv_reg_funcs[])(void) __initdata = {
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#ifdef CONFIG_OMAP4_DSS_HDMI
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hdmi4_init_platform_driver,
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#endif
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#ifdef CONFIG_OMAP5_DSS_HDMI
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hdmi5_init_platform_driver,
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#endif
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};
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static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = {
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@ -289,6 +292,9 @@ static void (*dss_output_drv_unreg_funcs[])(void) __exitdata = {
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#ifdef CONFIG_OMAP4_DSS_HDMI
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hdmi4_uninit_platform_driver,
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#endif
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#ifdef CONFIG_OMAP5_DSS_HDMI
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hdmi5_uninit_platform_driver,
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#endif
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};
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static bool dss_output_drv_loaded[ARRAY_SIZE(dss_output_drv_reg_funcs)];
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@ -419,6 +419,9 @@ void venc_uninit_platform_driver(void) __exit;
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int hdmi4_init_platform_driver(void) __init;
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void hdmi4_uninit_platform_driver(void) __exit;
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int hdmi5_init_platform_driver(void) __init;
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void hdmi5_uninit_platform_driver(void) __exit;
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/* RFBI */
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int rfbi_init_platform_driver(void) __init;
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void rfbi_uninit_platform_driver(void) __exit;
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@ -431,7 +431,7 @@ struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);
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int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
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struct hdmi_phy_data *phy);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
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int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
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int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
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int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
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@ -0,0 +1,829 @@
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/*
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* HDMI driver for OMAP5
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*
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* Copyright (C) 2014 Texas Instruments Incorporated
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*
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* Authors:
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* Yong Zhi
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* Mythri pk
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* Archit Taneja <archit@ti.com>
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* Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "HDMI"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/regulator/consumer.h>
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#include <video/omapdss.h>
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#include "hdmi5_core.h"
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#include "dss.h"
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#include "dss_features.h"
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static struct {
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struct mutex lock;
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struct platform_device *pdev;
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struct hdmi_wp_data wp;
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struct hdmi_pll_data pll;
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struct hdmi_phy_data phy;
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struct hdmi_core_data core;
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struct hdmi_config cfg;
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struct clk *sys_clk;
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struct regulator *vdda_reg;
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bool core_enabled;
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struct omap_dss_device output;
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} hdmi;
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static int hdmi_runtime_get(void)
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{
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int r;
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DSSDBG("hdmi_runtime_get\n");
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r = pm_runtime_get_sync(&hdmi.pdev->dev);
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WARN_ON(r < 0);
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if (r < 0)
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return r;
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return 0;
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}
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static void hdmi_runtime_put(void)
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{
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int r;
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DSSDBG("hdmi_runtime_put\n");
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r = pm_runtime_put_sync(&hdmi.pdev->dev);
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WARN_ON(r < 0 && r != -ENOSYS);
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}
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static irqreturn_t hdmi_irq_handler(int irq, void *data)
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{
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struct hdmi_wp_data *wp = data;
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u32 irqstatus;
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irqstatus = hdmi_wp_get_irqstatus(wp);
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hdmi_wp_set_irqstatus(wp, irqstatus);
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if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
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irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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u32 v;
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/*
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* If we get both connect and disconnect interrupts at the same
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* time, turn off the PHY, clear interrupts, and restart, which
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* raises connect interrupt if a cable is connected, or nothing
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* if cable is not connected.
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*/
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
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/*
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* We always get bogus CONNECT & DISCONNECT interrupts when
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* setting the PHY to LDOON. To ignore those, we force the RXDET
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* line to 0 until the PHY power state has been changed.
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*/
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v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
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v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
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v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
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hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
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hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
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HDMI_IRQ_LINK_DISCONNECT);
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
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} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
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} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
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hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
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}
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return IRQ_HANDLED;
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}
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static int hdmi_init_regulator(void)
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{
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int r;
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struct regulator *reg;
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if (hdmi.vdda_reg != NULL)
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return 0;
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reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
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if (IS_ERR(reg)) {
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DSSERR("can't get VDDA regulator\n");
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return PTR_ERR(reg);
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}
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if (regulator_can_change_voltage(reg)) {
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r = regulator_set_voltage(reg, 1800000, 1800000);
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if (r) {
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devm_regulator_put(reg);
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DSSWARN("can't set the regulator voltage\n");
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return r;
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}
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}
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hdmi.vdda_reg = reg;
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return 0;
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}
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static int hdmi_power_on_core(struct omap_dss_device *dssdev)
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{
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int r;
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r = regulator_enable(hdmi.vdda_reg);
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if (r)
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return r;
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r = hdmi_runtime_get();
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if (r)
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goto err_runtime_get;
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/* Make selection of HDMI in DSS */
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dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
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hdmi.core_enabled = true;
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return 0;
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err_runtime_get:
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regulator_disable(hdmi.vdda_reg);
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return r;
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}
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static void hdmi_power_off_core(struct omap_dss_device *dssdev)
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{
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hdmi.core_enabled = false;
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hdmi_runtime_put();
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regulator_disable(hdmi.vdda_reg);
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}
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static int hdmi_power_on_full(struct omap_dss_device *dssdev)
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{
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int r;
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struct omap_video_timings *p;
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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unsigned long phy;
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r = hdmi_power_on_core(dssdev);
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if (r)
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return r;
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p = &hdmi.cfg.timings;
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DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
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/* the functions below use kHz pixel clock. TODO: change to Hz */
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phy = p->pixelclock / 1000;
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hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
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/* disable and clear irqs */
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hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
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hdmi_wp_set_irqstatus(&hdmi.wp,
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hdmi_wp_get_irqstatus(&hdmi.wp));
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/* config the PLL and PHY hdmi_set_pll_pwrfirst */
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r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
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if (r) {
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DSSDBG("Failed to lock PLL\n");
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goto err_pll_enable;
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}
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r = hdmi_phy_configure(&hdmi.phy, &hdmi.cfg);
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if (r) {
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DSSDBG("Failed to start PHY\n");
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goto err_phy_cfg;
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}
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r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
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if (r)
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goto err_phy_pwr;
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hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
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/* bypass TV gamma table */
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dispc_enable_gamma_table(0);
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/* tv size */
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dss_mgr_set_timings(mgr, p);
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r = hdmi_wp_video_start(&hdmi.wp);
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if (r)
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goto err_vid_enable;
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r = dss_mgr_enable(mgr);
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if (r)
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goto err_mgr_enable;
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hdmi_wp_set_irqenable(&hdmi.wp,
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HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
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return 0;
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err_mgr_enable:
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hdmi_wp_video_stop(&hdmi.wp);
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err_vid_enable:
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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err_phy_pwr:
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err_phy_cfg:
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hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
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err_pll_enable:
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hdmi_power_off_core(dssdev);
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return -EIO;
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}
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static void hdmi_power_off_full(struct omap_dss_device *dssdev)
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{
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struct omap_overlay_manager *mgr = hdmi.output.manager;
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hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
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dss_mgr_disable(mgr);
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hdmi_wp_video_stop(&hdmi.wp);
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hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
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hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
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hdmi_power_off_core(dssdev);
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}
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static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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struct omap_dss_device *out = &hdmi.output;
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if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
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return -EINVAL;
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return 0;
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}
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static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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struct hdmi_cm cm;
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const struct hdmi_config *t;
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mutex_lock(&hdmi.lock);
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cm = hdmi_get_code(timings);
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hdmi.cfg.cm = cm;
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t = hdmi_get_timings(cm.mode, cm.code);
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if (t != NULL) {
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hdmi.cfg = *t;
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dispc_set_tv_pclk(t->timings.pixelclock);
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} else {
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hdmi.cfg.timings = *timings;
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hdmi.cfg.cm.code = 0;
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hdmi.cfg.cm.mode = HDMI_DVI;
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dispc_set_tv_pclk(timings->pixelclock);
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}
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DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ?
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"DVI" : "HDMI", hdmi.cfg.cm.code);
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mutex_unlock(&hdmi.lock);
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}
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static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
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struct omap_video_timings *timings)
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{
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const struct hdmi_config *cfg;
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struct hdmi_cm cm = hdmi.cfg.cm;
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cfg = hdmi_get_timings(cm.mode, cm.code);
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if (cfg == NULL)
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cfg = hdmi_default_timing();
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memcpy(timings, &cfg->timings, sizeof(cfg->timings));
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}
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static void hdmi_dump_regs(struct seq_file *s)
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{
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mutex_lock(&hdmi.lock);
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if (hdmi_runtime_get()) {
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mutex_unlock(&hdmi.lock);
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return;
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}
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hdmi_wp_dump(&hdmi.wp, s);
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hdmi_pll_dump(&hdmi.pll, s);
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hdmi_phy_dump(&hdmi.phy, s);
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hdmi5_core_dump(&hdmi.core, s);
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hdmi_runtime_put();
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mutex_unlock(&hdmi.lock);
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}
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static int read_edid(u8 *buf, int len)
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{
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int r;
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int idlemode;
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mutex_lock(&hdmi.lock);
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r = hdmi_runtime_get();
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BUG_ON(r);
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idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
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/* No-idle mode */
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REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
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r = hdmi5_read_edid(&hdmi.core, buf, len);
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REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
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hdmi_runtime_put();
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mutex_unlock(&hdmi.lock);
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return r;
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}
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static int hdmi_display_enable(struct omap_dss_device *dssdev)
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{
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struct omap_dss_device *out = &hdmi.output;
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int r = 0;
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DSSDBG("ENTER hdmi_display_enable\n");
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||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
if (out == NULL || out->manager == NULL) {
|
||||
DSSERR("failed to enable display: no output/manager\n");
|
||||
r = -ENODEV;
|
||||
goto err0;
|
||||
}
|
||||
|
||||
r = hdmi_power_on_full(dssdev);
|
||||
if (r) {
|
||||
DSSERR("failed to power on device\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return 0;
|
||||
|
||||
err0:
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return r;
|
||||
}
|
||||
|
||||
static void hdmi_display_disable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
DSSDBG("Enter hdmi_display_disable\n");
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
hdmi_power_off_full(dssdev);
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
}
|
||||
|
||||
static int hdmi_core_enable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
int r = 0;
|
||||
|
||||
DSSDBG("ENTER omapdss_hdmi_core_enable\n");
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
r = hdmi_power_on_core(dssdev);
|
||||
if (r) {
|
||||
DSSERR("failed to power on device\n");
|
||||
goto err0;
|
||||
}
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return 0;
|
||||
|
||||
err0:
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return r;
|
||||
}
|
||||
|
||||
static void hdmi_core_disable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
DSSDBG("Enter omapdss_hdmi_core_disable\n");
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
hdmi_power_off_core(dssdev);
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
}
|
||||
|
||||
static int hdmi_get_clocks(struct platform_device *pdev)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = devm_clk_get(&pdev->dev, "sys_clk");
|
||||
if (IS_ERR(clk)) {
|
||||
DSSERR("can't get sys_clk\n");
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
hdmi.sys_clk = clk;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_connect(struct omap_dss_device *dssdev,
|
||||
struct omap_dss_device *dst)
|
||||
{
|
||||
struct omap_overlay_manager *mgr;
|
||||
int r;
|
||||
|
||||
r = hdmi_init_regulator();
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
|
||||
if (!mgr)
|
||||
return -ENODEV;
|
||||
|
||||
r = dss_mgr_connect(mgr, dssdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = omapdss_output_set_device(dssdev, dst);
|
||||
if (r) {
|
||||
DSSERR("failed to connect output to new device: %s\n",
|
||||
dst->name);
|
||||
dss_mgr_disconnect(mgr, dssdev);
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hdmi_disconnect(struct omap_dss_device *dssdev,
|
||||
struct omap_dss_device *dst)
|
||||
{
|
||||
WARN_ON(dst != dssdev->dst);
|
||||
|
||||
if (dst != dssdev->dst)
|
||||
return;
|
||||
|
||||
omapdss_output_unset_device(dssdev);
|
||||
|
||||
if (dssdev->manager)
|
||||
dss_mgr_disconnect(dssdev->manager, dssdev);
|
||||
}
|
||||
|
||||
static int hdmi_read_edid(struct omap_dss_device *dssdev,
|
||||
u8 *edid, int len)
|
||||
{
|
||||
bool need_enable;
|
||||
int r;
|
||||
|
||||
need_enable = hdmi.core_enabled == false;
|
||||
|
||||
if (need_enable) {
|
||||
r = hdmi_core_enable(dssdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = read_edid(edid, len);
|
||||
|
||||
if (need_enable)
|
||||
hdmi_core_disable(dssdev);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
|
||||
static int hdmi_audio_enable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
|
||||
r = -EPERM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
r = hdmi_wp_audio_enable(&hdmi.wp, true);
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return r;
|
||||
}
|
||||
|
||||
static void hdmi_audio_disable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
hdmi_wp_audio_enable(&hdmi.wp, false);
|
||||
}
|
||||
|
||||
static int hdmi_audio_start(struct omap_dss_device *dssdev)
|
||||
{
|
||||
return hdmi_wp_audio_core_req_enable(&hdmi.wp, true);
|
||||
}
|
||||
|
||||
static void hdmi_audio_stop(struct omap_dss_device *dssdev)
|
||||
{
|
||||
hdmi_wp_audio_core_req_enable(&hdmi.wp, false);
|
||||
}
|
||||
|
||||
static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
|
||||
{
|
||||
bool r;
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return r;
|
||||
}
|
||||
|
||||
static int hdmi_audio_config(struct omap_dss_device *dssdev,
|
||||
struct omap_dss_audio *audio)
|
||||
{
|
||||
int r;
|
||||
u32 pclk = hdmi.cfg.timings.pixelclock;
|
||||
|
||||
mutex_lock(&hdmi.lock);
|
||||
|
||||
if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
|
||||
r = -EPERM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
mutex_unlock(&hdmi.lock);
|
||||
return r;
|
||||
}
|
||||
#else
|
||||
static int hdmi_audio_enable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
static void hdmi_audio_disable(struct omap_dss_device *dssdev)
|
||||
{
|
||||
}
|
||||
|
||||
static int hdmi_audio_start(struct omap_dss_device *dssdev)
|
||||
{
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
static void hdmi_audio_stop(struct omap_dss_device *dssdev)
|
||||
{
|
||||
}
|
||||
|
||||
static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static int hdmi_audio_config(struct omap_dss_device *dssdev,
|
||||
struct omap_dss_audio *audio)
|
||||
{
|
||||
return -EPERM;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct omapdss_hdmi_ops hdmi_ops = {
|
||||
.connect = hdmi_connect,
|
||||
.disconnect = hdmi_disconnect,
|
||||
|
||||
.enable = hdmi_display_enable,
|
||||
.disable = hdmi_display_disable,
|
||||
|
||||
.check_timings = hdmi_display_check_timing,
|
||||
.set_timings = hdmi_display_set_timing,
|
||||
.get_timings = hdmi_display_get_timings,
|
||||
|
||||
.read_edid = hdmi_read_edid,
|
||||
|
||||
.audio_enable = hdmi_audio_enable,
|
||||
.audio_disable = hdmi_audio_disable,
|
||||
.audio_start = hdmi_audio_start,
|
||||
.audio_stop = hdmi_audio_stop,
|
||||
.audio_supported = hdmi_audio_supported,
|
||||
.audio_config = hdmi_audio_config,
|
||||
};
|
||||
|
||||
static void hdmi_init_output(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_dss_device *out = &hdmi.output;
|
||||
|
||||
out->dev = &pdev->dev;
|
||||
out->id = OMAP_DSS_OUTPUT_HDMI;
|
||||
out->output_type = OMAP_DISPLAY_TYPE_HDMI;
|
||||
out->name = "hdmi.0";
|
||||
out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
|
||||
out->ops.hdmi = &hdmi_ops;
|
||||
out->owner = THIS_MODULE;
|
||||
|
||||
omapdss_register_output(out);
|
||||
}
|
||||
|
||||
static void __exit hdmi_uninit_output(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_dss_device *out = &hdmi.output;
|
||||
|
||||
omapdss_unregister_output(out);
|
||||
}
|
||||
|
||||
static int hdmi_probe_of(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *ep;
|
||||
int r;
|
||||
|
||||
ep = omapdss_of_get_first_endpoint(node);
|
||||
if (!ep)
|
||||
return 0;
|
||||
|
||||
r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
|
||||
if (r)
|
||||
goto err;
|
||||
|
||||
of_node_put(ep);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
of_node_put(ep);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* HDMI HW IP initialisation */
|
||||
static int omapdss_hdmihw_probe(struct platform_device *pdev)
|
||||
{
|
||||
int r;
|
||||
int irq;
|
||||
|
||||
hdmi.pdev = pdev;
|
||||
|
||||
mutex_init(&hdmi.lock);
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
r = hdmi_probe_of(pdev);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
r = hdmi_wp_init(pdev, &hdmi.wp);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi_pll_init(pdev, &hdmi.pll);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi_phy_init(pdev, &hdmi.phy);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi5_core_init(pdev, &hdmi.core);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = hdmi_get_clocks(pdev);
|
||||
if (r) {
|
||||
DSSERR("can't get clocks\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
DSSERR("platform_get_irq failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
r = devm_request_threaded_irq(&pdev->dev, irq,
|
||||
NULL, hdmi_irq_handler,
|
||||
IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
|
||||
if (r) {
|
||||
DSSERR("HDMI IRQ request failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
hdmi_init_output(pdev);
|
||||
|
||||
dss_debugfs_create_file("hdmi", hdmi_dump_regs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
|
||||
{
|
||||
hdmi_uninit_output(pdev);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
clk_disable_unprepare(hdmi.sys_clk);
|
||||
|
||||
dispc_runtime_put();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_runtime_resume(struct device *dev)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = dispc_runtime_get();
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
clk_prepare_enable(hdmi.sys_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops hdmi_pm_ops = {
|
||||
.runtime_suspend = hdmi_runtime_suspend,
|
||||
.runtime_resume = hdmi_runtime_resume,
|
||||
};
|
||||
|
||||
static const struct of_device_id hdmi_of_match[] = {
|
||||
{ .compatible = "ti,omap5-hdmi", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver omapdss_hdmihw_driver = {
|
||||
.probe = omapdss_hdmihw_probe,
|
||||
.remove = __exit_p(omapdss_hdmihw_remove),
|
||||
.driver = {
|
||||
.name = "omapdss_hdmi5",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = &hdmi_pm_ops,
|
||||
.of_match_table = hdmi_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
int __init hdmi5_init_platform_driver(void)
|
||||
{
|
||||
return platform_driver_register(&omapdss_hdmihw_driver);
|
||||
}
|
||||
|
||||
void __exit hdmi5_uninit_platform_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&omapdss_hdmihw_driver);
|
||||
}
|
||||
|
|
@ -0,0 +1,922 @@
|
|||
/*
|
||||
* OMAP5 HDMI CORE IP driver library
|
||||
*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated
|
||||
*
|
||||
* Authors:
|
||||
* Yong Zhi
|
||||
* Mythri pk
|
||||
* Archit Taneja <archit@ti.com>
|
||||
* Tomi Valkeinen <tomi.valkeinen@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
|
||||
#include <sound/asound.h>
|
||||
#include <sound/asoundef.h>
|
||||
#endif
|
||||
|
||||
#include "hdmi5_core.h"
|
||||
|
||||
/* only 24 bit color depth used for now */
|
||||
static const struct csc_table csc_table_deepcolor[] = {
|
||||
/* HDMI_DEEP_COLOR_24BIT */
|
||||
[0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
|
||||
/* HDMI_DEEP_COLOR_30BIT */
|
||||
[1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
|
||||
/* HDMI_DEEP_COLOR_36BIT */
|
||||
[2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
|
||||
/* FULL RANGE */
|
||||
[3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
|
||||
};
|
||||
|
||||
static void hdmi_core_ddc_init(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
|
||||
const unsigned ss_scl_high = 4000; /* ns */
|
||||
const unsigned ss_scl_low = 4700; /* ns */
|
||||
const unsigned fs_scl_high = 600; /* ns */
|
||||
const unsigned fs_scl_low = 1300; /* ns */
|
||||
const unsigned sda_hold = 300; /* ns */
|
||||
const unsigned sfr_div = 10;
|
||||
unsigned long long sfr;
|
||||
unsigned v;
|
||||
|
||||
sfr = iclk / sfr_div; /* SFR_DIV */
|
||||
sfr /= 1000; /* SFR clock in kHz */
|
||||
|
||||
/* Reset */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
|
||||
if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
|
||||
0, 0, 1) != 1)
|
||||
DSSERR("HDMI I2CM reset failed\n");
|
||||
|
||||
/* Standard (0) or Fast (1) Mode */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
|
||||
|
||||
/* Standard Mode SCL High counter */
|
||||
v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
|
||||
(v >> 8) & 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
|
||||
v & 0xff, 7, 0);
|
||||
|
||||
/* Standard Mode SCL Low counter */
|
||||
v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
|
||||
(v >> 8) & 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
|
||||
v & 0xff, 7, 0);
|
||||
|
||||
/* Fast Mode SCL High Counter */
|
||||
v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
|
||||
(v >> 8) & 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
|
||||
v & 0xff, 7, 0);
|
||||
|
||||
/* Fast Mode SCL Low Counter */
|
||||
v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
|
||||
(v >> 8) & 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
|
||||
v & 0xff, 7, 0);
|
||||
|
||||
/* SDA Hold Time */
|
||||
v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
|
||||
|
||||
/* NACK_POL to high */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
|
||||
|
||||
/* NACK_MASK to unmasked */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
|
||||
|
||||
/* ARBITRATION_POL to high */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
|
||||
|
||||
/* ARBITRATION_MASK to unmasked */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
|
||||
|
||||
/* DONE_POL to high */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
|
||||
|
||||
/* DONE_MASK to unmasked */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
|
||||
}
|
||||
|
||||
static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
/* Mask I2C interrupts */
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
|
||||
}
|
||||
|
||||
static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
u8 cur_addr;
|
||||
char checksum = 0;
|
||||
const int retries = 1000;
|
||||
u8 seg_ptr = ext / 2;
|
||||
u8 edidbase = ((ext % 2) * 0x80);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
|
||||
|
||||
/*
|
||||
* TODO: We use polling here, although we probably should use proper
|
||||
* interrupts.
|
||||
*/
|
||||
for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
|
||||
int i;
|
||||
|
||||
/* clear ERROR and DONE */
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
|
||||
edidbase + cur_addr, 7, 0);
|
||||
|
||||
if (seg_ptr)
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
|
||||
else
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
|
||||
|
||||
for (i = 0; i < retries; ++i) {
|
||||
u32 stat;
|
||||
|
||||
stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
|
||||
|
||||
/* I2CM_ERROR */
|
||||
if (stat & 1) {
|
||||
DSSERR("HDMI I2C Master Error\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
/* I2CM_DONE */
|
||||
if (stat & (1 << 1))
|
||||
break;
|
||||
|
||||
usleep_range(250, 1000);
|
||||
}
|
||||
|
||||
if (i == retries) {
|
||||
DSSERR("HDMI I2C timeout reading EDID\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
|
||||
checksum += pedid[cur_addr];
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
|
||||
{
|
||||
int r, n, i;
|
||||
int max_ext_blocks = (len / 128) - 1;
|
||||
|
||||
if (len < 128)
|
||||
return -EINVAL;
|
||||
|
||||
hdmi_core_ddc_init(core);
|
||||
|
||||
r = hdmi_core_ddc_edid(core, edid, 0);
|
||||
if (r)
|
||||
goto out;
|
||||
|
||||
n = edid[0x7e];
|
||||
|
||||
if (n > max_ext_blocks)
|
||||
n = max_ext_blocks;
|
||||
|
||||
for (i = 1; i <= n; i++) {
|
||||
r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
|
||||
if (r)
|
||||
goto out;
|
||||
}
|
||||
|
||||
out:
|
||||
hdmi_core_ddc_uninit(core);
|
||||
|
||||
return r ? r : len;
|
||||
}
|
||||
|
||||
void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
|
||||
{
|
||||
|
||||
#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
|
||||
hdmi_read_reg(core->base, r))
|
||||
|
||||
DUMPCORE(HDMI_CORE_FC_INVIDCONF);
|
||||
DUMPCORE(HDMI_CORE_FC_INHACTIV0);
|
||||
DUMPCORE(HDMI_CORE_FC_INHACTIV1);
|
||||
DUMPCORE(HDMI_CORE_FC_INHBLANK0);
|
||||
DUMPCORE(HDMI_CORE_FC_INHBLANK1);
|
||||
DUMPCORE(HDMI_CORE_FC_INVACTIV0);
|
||||
DUMPCORE(HDMI_CORE_FC_INVACTIV1);
|
||||
DUMPCORE(HDMI_CORE_FC_INVBLANK);
|
||||
DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
|
||||
DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
|
||||
DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
|
||||
DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
|
||||
DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
|
||||
DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
|
||||
DUMPCORE(HDMI_CORE_FC_CTRLDUR);
|
||||
DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
|
||||
DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
|
||||
DUMPCORE(HDMI_CORE_FC_CH0PREAM);
|
||||
DUMPCORE(HDMI_CORE_FC_CH1PREAM);
|
||||
DUMPCORE(HDMI_CORE_FC_CH2PREAM);
|
||||
DUMPCORE(HDMI_CORE_FC_AVICONF0);
|
||||
DUMPCORE(HDMI_CORE_FC_AVICONF1);
|
||||
DUMPCORE(HDMI_CORE_FC_AVICONF2);
|
||||
DUMPCORE(HDMI_CORE_FC_AVIVID);
|
||||
DUMPCORE(HDMI_CORE_FC_PRCONF);
|
||||
|
||||
DUMPCORE(HDMI_CORE_MC_CLKDIS);
|
||||
DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
|
||||
DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
|
||||
DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
|
||||
DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
|
||||
|
||||
DUMPCORE(HDMI_CORE_I2CM_SLAVE);
|
||||
DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
|
||||
DUMPCORE(HDMI_CORE_I2CM_DATAO);
|
||||
DUMPCORE(HDMI_CORE_I2CM_DATAI);
|
||||
DUMPCORE(HDMI_CORE_I2CM_OPERATION);
|
||||
DUMPCORE(HDMI_CORE_I2CM_INT);
|
||||
DUMPCORE(HDMI_CORE_I2CM_CTLINT);
|
||||
DUMPCORE(HDMI_CORE_I2CM_DIV);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
|
||||
DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
|
||||
}
|
||||
|
||||
static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
|
||||
struct hdmi_core_infoframe_avi *avi_cfg,
|
||||
struct hdmi_config *cfg)
|
||||
{
|
||||
DSSDBG("hdmi_core_init\n");
|
||||
|
||||
/* video core */
|
||||
video_cfg->data_enable_pol = 1; /* It is always 1*/
|
||||
video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
|
||||
video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
|
||||
video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
|
||||
video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
|
||||
video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
|
||||
video_cfg->hblank = cfg->timings.hfp +
|
||||
cfg->timings.hbp + cfg->timings.hsw - 1;
|
||||
video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
|
||||
video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
|
||||
video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
|
||||
video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
|
||||
video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
|
||||
video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
|
||||
video_cfg->vblank = cfg->timings.vsw +
|
||||
cfg->timings.vfp + cfg->timings.vbp;
|
||||
video_cfg->v_fc_config.cm.mode = cfg->cm.mode;
|
||||
video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
|
||||
|
||||
/* info frame */
|
||||
avi_cfg->db1_format = 0;
|
||||
avi_cfg->db1_active_info = 0;
|
||||
avi_cfg->db1_bar_info_dv = 0;
|
||||
avi_cfg->db1_scan_info = 0;
|
||||
avi_cfg->db2_colorimetry = 0;
|
||||
avi_cfg->db2_aspect_ratio = 0;
|
||||
avi_cfg->db2_active_fmt_ar = 0;
|
||||
avi_cfg->db3_itc = 0;
|
||||
avi_cfg->db3_ec = 0;
|
||||
avi_cfg->db3_q_range = 0;
|
||||
avi_cfg->db3_nup_scaling = 0;
|
||||
avi_cfg->db4_videocode = 0;
|
||||
avi_cfg->db5_pixel_repeat = 0;
|
||||
avi_cfg->db6_7_line_eoftop = 0;
|
||||
avi_cfg->db8_9_line_sofbottom = 0;
|
||||
avi_cfg->db10_11_pixel_eofleft = 0;
|
||||
avi_cfg->db12_13_pixel_sofright = 0;
|
||||
}
|
||||
|
||||
/* DSS_HDMI_CORE_VIDEO_CONFIG */
|
||||
static void hdmi_core_video_config(struct hdmi_core_data *core,
|
||||
struct hdmi_core_vid_config *cfg)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
unsigned char r = 0;
|
||||
bool vsync_pol, hsync_pol;
|
||||
|
||||
vsync_pol =
|
||||
cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
hsync_pol =
|
||||
cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
|
||||
|
||||
/* Set hsync, vsync and data-enable polarity */
|
||||
r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
|
||||
r = FLD_MOD(r, vsync_pol, 6, 6);
|
||||
r = FLD_MOD(r, hsync_pol, 5, 5);
|
||||
r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
|
||||
r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
|
||||
r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
|
||||
|
||||
/* set x resolution */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
|
||||
cfg->v_fc_config.timings.x_res >> 8, 4, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
|
||||
cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
|
||||
|
||||
/* set y resolution */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
|
||||
cfg->v_fc_config.timings.y_res >> 8, 4, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
|
||||
cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
|
||||
|
||||
/* set horizontal blanking pixels */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
|
||||
|
||||
/* set vertial blanking pixels */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
|
||||
|
||||
/* set horizontal sync offset */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
|
||||
cfg->v_fc_config.timings.hfp >> 8, 4, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
|
||||
cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
|
||||
|
||||
/* set vertical sync offset */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
|
||||
cfg->v_fc_config.timings.vfp, 7, 0);
|
||||
|
||||
/* set horizontal sync pulse width */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
|
||||
(cfg->v_fc_config.timings.hsw >> 8), 1, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
|
||||
cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
|
||||
|
||||
/* set vertical sync pulse width */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
|
||||
cfg->v_fc_config.timings.vsw, 5, 0);
|
||||
|
||||
/* select DVI mode */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
|
||||
cfg->v_fc_config.cm.mode, 3, 3);
|
||||
}
|
||||
|
||||
static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
int clr_depth = 0; /* 24 bit color depth */
|
||||
|
||||
/* COLOR_DEPTH */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
|
||||
/* BYPASS_EN */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
|
||||
/* PP_EN */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
|
||||
/* YCC422_EN */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
|
||||
/* PP_STUFFING */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
|
||||
/* YCC422_STUFFING */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
|
||||
/* OUTPUT_SELECTOR */
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
|
||||
}
|
||||
|
||||
static void hdmi_core_config_csc(struct hdmi_core_data *core)
|
||||
{
|
||||
int clr_depth = 0; /* 24 bit color depth */
|
||||
|
||||
/* CSC_COLORDEPTH */
|
||||
REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
|
||||
}
|
||||
|
||||
static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
|
||||
{
|
||||
int video_mapping = 1; /* for 24 bit color depth */
|
||||
|
||||
/* VIDEO_MAPPING */
|
||||
REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
|
||||
}
|
||||
|
||||
static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
struct hdmi_core_infoframe_avi avi = core->avi_cfg;
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_format, 1, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_active_info, 6, 6);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_bar_info_dv, 3, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_scan_info, 5, 4);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_colorimetry, 7, 6);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_aspect_ratio, 5, 4);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_active_fmt_ar, 3, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_itc, 7, 7);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_ec, 6, 4);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_q_range, 3, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_nup_scaling, 1, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AVIVID, avi.db4_videocode, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, avi.db5_pixel_repeat, 3, 0);
|
||||
}
|
||||
|
||||
static void hdmi_core_csc_config(struct hdmi_core_data *core,
|
||||
struct csc_table csc_coeff)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
|
||||
}
|
||||
|
||||
static void hdmi_core_configure_range(struct hdmi_core_data *core)
|
||||
{
|
||||
struct csc_table csc_coeff = { 0 };
|
||||
|
||||
/* support limited range with 24 bit color depth for now */
|
||||
csc_coeff = csc_table_deepcolor[0];
|
||||
core->avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_LR;
|
||||
|
||||
hdmi_core_csc_config(core, csc_coeff);
|
||||
hdmi_core_aux_infoframe_avi_config(core);
|
||||
}
|
||||
|
||||
static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
DSSDBG("hdmi_core_enable_video_path\n");
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
|
||||
}
|
||||
|
||||
static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
/* Master IRQ mask */
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
|
||||
|
||||
/* Mask all the interrupts in HDMI core */
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
|
||||
|
||||
/* Clear all the current interrupt bits */
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
|
||||
}
|
||||
|
||||
static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
|
||||
{
|
||||
/* Unmute interrupts */
|
||||
REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
|
||||
}
|
||||
|
||||
int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||
struct hdmi_config *cfg)
|
||||
{
|
||||
struct omap_video_timings video_timing;
|
||||
struct hdmi_video_format video_format;
|
||||
struct hdmi_core_vid_config v_core_cfg;
|
||||
struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg;
|
||||
|
||||
hdmi_core_mask_interrupts(core);
|
||||
|
||||
hdmi_core_init(&v_core_cfg, avi_cfg, cfg);
|
||||
|
||||
hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
|
||||
|
||||
hdmi_wp_video_config_timing(wp, &video_timing);
|
||||
|
||||
/* video config */
|
||||
video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
|
||||
|
||||
hdmi_wp_video_config_format(wp, &video_format);
|
||||
|
||||
hdmi_wp_video_config_interface(wp, &video_timing);
|
||||
|
||||
hdmi_core_configure_range(core);
|
||||
|
||||
/*
|
||||
* configure core video part, set software reset in the core
|
||||
*/
|
||||
v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
|
||||
|
||||
hdmi_core_video_config(core, &v_core_cfg);
|
||||
|
||||
hdmi_core_config_video_packetizer(core);
|
||||
hdmi_core_config_csc(core);
|
||||
hdmi_core_config_video_sampler(core);
|
||||
|
||||
/*
|
||||
* configure packet info frame video see doc CEA861-D page 65
|
||||
*/
|
||||
avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
|
||||
avi_cfg->db1_active_info =
|
||||
HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
|
||||
avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
|
||||
avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
|
||||
avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
|
||||
avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
|
||||
avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
|
||||
avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
|
||||
avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
|
||||
avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
|
||||
avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
|
||||
avi_cfg->db4_videocode = cfg->cm.code;
|
||||
avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
|
||||
avi_cfg->db6_7_line_eoftop = 0;
|
||||
avi_cfg->db8_9_line_sofbottom = 0;
|
||||
avi_cfg->db10_11_pixel_eofleft = 0;
|
||||
avi_cfg->db12_13_pixel_sofright = 0;
|
||||
|
||||
hdmi_core_aux_infoframe_avi_config(core);
|
||||
|
||||
hdmi_core_enable_video_path(core);
|
||||
|
||||
hdmi_core_enable_interrupts(core);
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
|
||||
|
||||
static void hdmi5_core_audio_config(struct hdmi_core_data *core,
|
||||
struct hdmi_core_audio_config *cfg)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
u8 val;
|
||||
|
||||
/* Mute audio before configuring */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
|
||||
|
||||
/* Set the N parameter */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
|
||||
|
||||
/*
|
||||
* CTS manual mode. Automatic mode is not supported when using audio
|
||||
* parallel interface.
|
||||
*/
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
|
||||
|
||||
/* Layout of Audio Sample Packets: 2-channel or multichannels */
|
||||
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
|
||||
else
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
|
||||
|
||||
/* Configure IEC-609580 Validity bits */
|
||||
/* Channel 0 is valid */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
|
||||
|
||||
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
|
||||
val = 1;
|
||||
else
|
||||
val = 0;
|
||||
|
||||
/* Channels 1, 2 setting */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
|
||||
/* Channel 3 setting */
|
||||
if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
|
||||
val = 1;
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
|
||||
|
||||
/* Configure IEC-60958 User bits */
|
||||
/* TODO: should be set by user. */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
|
||||
|
||||
/* Configure IEC-60958 Channel Status word */
|
||||
/* CGMSA */
|
||||
val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
|
||||
|
||||
/* Copyright */
|
||||
val = (cfg->iec60958_cfg->status[0] &
|
||||
IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
|
||||
|
||||
/* Category */
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
|
||||
cfg->iec60958_cfg->status[1]);
|
||||
|
||||
/* PCM audio mode */
|
||||
val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
|
||||
|
||||
/* Source number */
|
||||
val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 4);
|
||||
|
||||
/* Channel number right 0 */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
|
||||
/* Channel number right 1*/
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
|
||||
/* Channel number right 2 */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
|
||||
/* Channel number right 3*/
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
|
||||
/* Channel number left 0 */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
|
||||
/* Channel number left 1*/
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
|
||||
/* Channel number left 2 */
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
|
||||
/* Channel number left 3*/
|
||||
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
|
||||
|
||||
/* Clock accuracy and sample rate */
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
|
||||
cfg->iec60958_cfg->status[3]);
|
||||
|
||||
/* Original sample rate and word length */
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
|
||||
cfg->iec60958_cfg->status[4]);
|
||||
|
||||
/* Enable FIFO empty and full interrupts */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
|
||||
|
||||
/* Configure GPA */
|
||||
/* select HBR/SPDIF interfaces */
|
||||
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
|
||||
/* select HBR/SPDIF interfaces */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
|
||||
/* enable two channels in GPA */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
|
||||
} else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
|
||||
/* select HBR/SPDIF interfaces */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
|
||||
/* enable six channels in GPA */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
|
||||
} else {
|
||||
/* select HBR/SPDIF interfaces */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
|
||||
/* enable eight channels in GPA */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
|
||||
}
|
||||
|
||||
/* disable HBR */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
|
||||
/* enable PCUV */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
|
||||
/* enable GPA FIFO full and empty mask */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
|
||||
/* set polarity of GPA FIFO empty interrupts */
|
||||
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
|
||||
|
||||
/* unmute audio */
|
||||
REG_FLD_MOD(core_sys_base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
|
||||
}
|
||||
|
||||
static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
|
||||
struct snd_cea_861_aud_if *info_aud)
|
||||
{
|
||||
void __iomem *base = core->base;
|
||||
|
||||
/* channel count and coding type fields in AUDICONF0 are swapped */
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
|
||||
(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
|
||||
(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
|
||||
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
|
||||
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3, info_aud->db5_dminh_lsv);
|
||||
}
|
||||
|
||||
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||
struct omap_dss_audio *audio, u32 pclk)
|
||||
{
|
||||
struct hdmi_audio_format audio_format;
|
||||
struct hdmi_audio_dma audio_dma;
|
||||
struct hdmi_core_audio_config core_cfg;
|
||||
int err, n, cts, channel_count;
|
||||
unsigned int fs_nr;
|
||||
bool word_length_16b = false;
|
||||
|
||||
if (!audio || !audio->iec || !audio->cea || !core)
|
||||
return -EINVAL;
|
||||
|
||||
core_cfg.iec60958_cfg = audio->iec;
|
||||
|
||||
if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
|
||||
(audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
|
||||
word_length_16b = true;
|
||||
|
||||
/* only 16-bit word length supported atm */
|
||||
if (!word_length_16b)
|
||||
return -EINVAL;
|
||||
|
||||
switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
|
||||
case IEC958_AES3_CON_FS_32000:
|
||||
fs_nr = 32000;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_44100:
|
||||
fs_nr = 44100;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_48000:
|
||||
fs_nr = 48000;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_88200:
|
||||
fs_nr = 88200;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_96000:
|
||||
fs_nr = 96000;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_176400:
|
||||
fs_nr = 176400;
|
||||
break;
|
||||
case IEC958_AES3_CON_FS_192000:
|
||||
fs_nr = 192000;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
|
||||
core_cfg.n = n;
|
||||
core_cfg.cts = cts;
|
||||
|
||||
/* Audio channels settings */
|
||||
channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
|
||||
+ 1;
|
||||
|
||||
if (channel_count == 2)
|
||||
core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
|
||||
else if (channel_count == 6)
|
||||
core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
|
||||
else
|
||||
core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
|
||||
|
||||
/* DMA settings */
|
||||
if (word_length_16b)
|
||||
audio_dma.transfer_size = 0x10;
|
||||
else
|
||||
audio_dma.transfer_size = 0x20;
|
||||
audio_dma.block_size = 0xC0;
|
||||
audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
|
||||
audio_dma.fifo_threshold = 0x20; /* in number of samples */
|
||||
|
||||
/* audio FIFO format settings for 16-bit samples*/
|
||||
audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
|
||||
audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
|
||||
audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
|
||||
|
||||
/* only LPCM atm */
|
||||
audio_format.type = HDMI_AUDIO_TYPE_LPCM;
|
||||
|
||||
/* disable start/stop signals of IEC 60958 blocks */
|
||||
audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
|
||||
|
||||
/* configure DMA and audio FIFO format*/
|
||||
hdmi_wp_audio_config_dma(wp, &audio_dma);
|
||||
hdmi_wp_audio_config_format(wp, &audio_format);
|
||||
|
||||
/* configure the core */
|
||||
hdmi5_core_audio_config(core, &core_cfg);
|
||||
|
||||
/* configure CEA 861 audio infoframe */
|
||||
hdmi5_core_audio_infoframe_cfg(core, audio->cea);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
|
||||
if (!res) {
|
||||
DSSERR("can't get CORE IORESOURCE_MEM HDMI\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
core->base = devm_request_and_ioremap(&pdev->dev, res);
|
||||
if (!core->base) {
|
||||
DSSERR("can't ioremap HDMI core\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* HDMI driver definition for TI OMAP5 processors.
|
||||
*
|
||||
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _HDMI5_CORE_H_
|
||||
#define _HDMI5_CORE_H_
|
||||
|
||||
#include "hdmi.h"
|
||||
|
||||
/* HDMI IP Core System */
|
||||
|
||||
/* HDMI Identification */
|
||||
#define HDMI_CORE_DESIGN_ID 0x00000
|
||||
#define HDMI_CORE_REVISION_ID 0x00004
|
||||
#define HDMI_CORE_PRODUCT_ID0 0x00008
|
||||
#define HDMI_CORE_PRODUCT_ID1 0x0000C
|
||||
#define HDMI_CORE_CONFIG0_ID 0x00010
|
||||
#define HDMI_CORE_CONFIG1_ID 0x00014
|
||||
#define HDMI_CORE_CONFIG2_ID 0x00018
|
||||
#define HDMI_CORE_CONFIG3_ID 0x0001C
|
||||
|
||||
/* HDMI Interrupt */
|
||||
#define HDMI_CORE_IH_FC_STAT0 0x00400
|
||||
#define HDMI_CORE_IH_FC_STAT1 0x00404
|
||||
#define HDMI_CORE_IH_FC_STAT2 0x00408
|
||||
#define HDMI_CORE_IH_AS_STAT0 0x0040C
|
||||
#define HDMI_CORE_IH_PHY_STAT0 0x00410
|
||||
#define HDMI_CORE_IH_I2CM_STAT0 0x00414
|
||||
#define HDMI_CORE_IH_CEC_STAT0 0x00418
|
||||
#define HDMI_CORE_IH_VP_STAT0 0x0041C
|
||||
#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420
|
||||
#define HDMI_CORE_IH_MUTE 0x007FC
|
||||
|
||||
/* HDMI Video Sampler */
|
||||
#define HDMI_CORE_TX_INVID0 0x00800
|
||||
#define HDMI_CORE_TX_INSTUFFING 0x00804
|
||||
#define HDMI_CORE_TX_RGYDATA0 0x00808
|
||||
#define HDMI_CORE_TX_RGYDATA1 0x0080C
|
||||
#define HDMI_CORE_TX_RCRDATA0 0x00810
|
||||
#define HDMI_CORE_TX_RCRDATA1 0x00814
|
||||
#define HDMI_CORE_TX_BCBDATA0 0x00818
|
||||
#define HDMI_CORE_TX_BCBDATA1 0x0081C
|
||||
|
||||
/* HDMI Video Packetizer */
|
||||
#define HDMI_CORE_VP_STATUS 0x02000
|
||||
#define HDMI_CORE_VP_PR_CD 0x02004
|
||||
#define HDMI_CORE_VP_STUFF 0x02008
|
||||
#define HDMI_CORE_VP_REMAP 0x0200C
|
||||
#define HDMI_CORE_VP_CONF 0x02010
|
||||
#define HDMI_CORE_VP_STAT 0x02014
|
||||
#define HDMI_CORE_VP_INT 0x02018
|
||||
#define HDMI_CORE_VP_MASK 0x0201C
|
||||
#define HDMI_CORE_VP_POL 0x02020
|
||||
|
||||
/* Frame Composer */
|
||||
#define HDMI_CORE_FC_INVIDCONF 0x04000
|
||||
#define HDMI_CORE_FC_INHACTIV0 0x04004
|
||||
#define HDMI_CORE_FC_INHACTIV1 0x04008
|
||||
#define HDMI_CORE_FC_INHBLANK0 0x0400C
|
||||
#define HDMI_CORE_FC_INHBLANK1 0x04010
|
||||
#define HDMI_CORE_FC_INVACTIV0 0x04014
|
||||
#define HDMI_CORE_FC_INVACTIV1 0x04018
|
||||
#define HDMI_CORE_FC_INVBLANK 0x0401C
|
||||
#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020
|
||||
#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024
|
||||
#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028
|
||||
#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C
|
||||
#define HDMI_CORE_FC_VSYNCINDELAY 0x04030
|
||||
#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034
|
||||
#define HDMI_CORE_FC_INFREQ0 0x04038
|
||||
#define HDMI_CORE_FC_INFREQ1 0x0403C
|
||||
#define HDMI_CORE_FC_INFREQ2 0x04040
|
||||
#define HDMI_CORE_FC_CTRLDUR 0x04044
|
||||
#define HDMI_CORE_FC_EXCTRLDUR 0x04048
|
||||
#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C
|
||||
#define HDMI_CORE_FC_CH0PREAM 0x04050
|
||||
#define HDMI_CORE_FC_CH1PREAM 0x04054
|
||||
#define HDMI_CORE_FC_CH2PREAM 0x04058
|
||||
#define HDMI_CORE_FC_AVICONF3 0x0405C
|
||||
#define HDMI_CORE_FC_GCP 0x04060
|
||||
#define HDMI_CORE_FC_AVICONF0 0x04064
|
||||
#define HDMI_CORE_FC_AVICONF1 0x04068
|
||||
#define HDMI_CORE_FC_AVICONF2 0x0406C
|
||||
#define HDMI_CORE_FC_AVIVID 0x04070
|
||||
#define HDMI_CORE_FC_AVIETB0 0x04074
|
||||
#define HDMI_CORE_FC_AVIETB1 0x04078
|
||||
#define HDMI_CORE_FC_AVISBB0 0x0407C
|
||||
#define HDMI_CORE_FC_AVISBB1 0x04080
|
||||
#define HDMI_CORE_FC_AVIELB0 0x04084
|
||||
#define HDMI_CORE_FC_AVIELB1 0x04088
|
||||
#define HDMI_CORE_FC_AVISRB0 0x0408C
|
||||
#define HDMI_CORE_FC_AVISRB1 0x04090
|
||||
#define HDMI_CORE_FC_AUDICONF0 0x04094
|
||||
#define HDMI_CORE_FC_AUDICONF1 0x04098
|
||||
#define HDMI_CORE_FC_AUDICONF2 0x0409C
|
||||
#define HDMI_CORE_FC_AUDICONF3 0x040A0
|
||||
#define HDMI_CORE_FC_VSDIEEEID0 0x040A4
|
||||
#define HDMI_CORE_FC_VSDSIZE 0x040A8
|
||||
#define HDMI_CORE_FC_VSDIEEEID1 0x040C0
|
||||
#define HDMI_CORE_FC_VSDIEEEID2 0x040C4
|
||||
#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8)
|
||||
#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128)
|
||||
#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148)
|
||||
#define HDMI_CORE_FC_SPDDEVICEINF 0x04188
|
||||
#define HDMI_CORE_FC_AUDSCONF 0x0418C
|
||||
#define HDMI_CORE_FC_AUDSSTAT 0x04190
|
||||
#define HDMI_CORE_FC_AUDSV 0x04194
|
||||
#define HDMI_CORE_FC_AUDSU 0x04198
|
||||
#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C)
|
||||
#define HDMI_CORE_FC_CTRLQHIGH 0x041CC
|
||||
#define HDMI_CORE_FC_CTRLQLOW 0x041D0
|
||||
#define HDMI_CORE_FC_ACP0 0x041D4
|
||||
#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208)
|
||||
#define HDMI_CORE_FC_ISCR1_0 0x04248
|
||||
#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C)
|
||||
#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C)
|
||||
#define HDMI_CORE_FC_DATAUTO0 0x042CC
|
||||
#define HDMI_CORE_FC_DATAUTO1 0x042D0
|
||||
#define HDMI_CORE_FC_DATAUTO2 0x042D4
|
||||
#define HDMI_CORE_FC_DATMAN 0x042D8
|
||||
#define HDMI_CORE_FC_DATAUTO3 0x042DC
|
||||
#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0)
|
||||
#define HDMI_CORE_FC_STAT0 0x04340
|
||||
#define HDMI_CORE_FC_INT0 0x04344
|
||||
#define HDMI_CORE_FC_MASK0 0x04348
|
||||
#define HDMI_CORE_FC_POL0 0x0434C
|
||||
#define HDMI_CORE_FC_STAT1 0x04350
|
||||
#define HDMI_CORE_FC_INT1 0x04354
|
||||
#define HDMI_CORE_FC_MASK1 0x04358
|
||||
#define HDMI_CORE_FC_POL1 0x0435C
|
||||
#define HDMI_CORE_FC_STAT2 0x04360
|
||||
#define HDMI_CORE_FC_INT2 0x04364
|
||||
#define HDMI_CORE_FC_MASK2 0x04368
|
||||
#define HDMI_CORE_FC_POL2 0x0436C
|
||||
#define HDMI_CORE_FC_PRCONF 0x04380
|
||||
#define HDMI_CORE_FC_GMD_STAT 0x04400
|
||||
#define HDMI_CORE_FC_GMD_EN 0x04404
|
||||
#define HDMI_CORE_FC_GMD_UP 0x04408
|
||||
#define HDMI_CORE_FC_GMD_CONF 0x0440C
|
||||
#define HDMI_CORE_FC_GMD_HB 0x04410
|
||||
#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414)
|
||||
#define HDMI_CORE_FC_DBGFORCE 0x04800
|
||||
#define HDMI_CORE_FC_DBGAUD0CH0 0x04804
|
||||
#define HDMI_CORE_FC_DBGAUD1CH0 0x04808
|
||||
#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C
|
||||
#define HDMI_CORE_FC_DBGAUD0CH1 0x04810
|
||||
#define HDMI_CORE_FC_DBGAUD1CH1 0x04814
|
||||
#define HDMI_CORE_FC_DBGAUD2CH1 0x04818
|
||||
#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C
|
||||
#define HDMI_CORE_FC_DBGAUD1CH2 0x04820
|
||||
#define HDMI_CORE_FC_DBGAUD2CH2 0x04824
|
||||
#define HDMI_CORE_FC_DBGAUD0CH3 0x04828
|
||||
#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C
|
||||
#define HDMI_CORE_FC_DBGAUD2CH3 0x04830
|
||||
#define HDMI_CORE_FC_DBGAUD0CH4 0x04834
|
||||
#define HDMI_CORE_FC_DBGAUD1CH4 0x04838
|
||||
#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C
|
||||
#define HDMI_CORE_FC_DBGAUD0CH5 0x04840
|
||||
#define HDMI_CORE_FC_DBGAUD1CH5 0x04844
|
||||
#define HDMI_CORE_FC_DBGAUD2CH5 0x04848
|
||||
#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C
|
||||
#define HDMI_CORE_FC_DBGAUD1CH6 0x04850
|
||||
#define HDMI_CORE_FC_DBGAUD2CH6 0x04854
|
||||
#define HDMI_CORE_FC_DBGAUD0CH7 0x04858
|
||||
#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C
|
||||
#define HDMI_CORE_FC_DBGAUD2CH7 0x04860
|
||||
#define HDMI_CORE_FC_DBGTMDS0 0x04864
|
||||
#define HDMI_CORE_FC_DBGTMDS1 0x04868
|
||||
#define HDMI_CORE_FC_DBGTMDS2 0x0486C
|
||||
#define HDMI_CORE_PHY_MASK0 0x0C018
|
||||
#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C
|
||||
#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0
|
||||
|
||||
/* HDMI Audio */
|
||||
#define HDMI_CORE_AUD_CONF0 0x0C400
|
||||
#define HDMI_CORE_AUD_CONF1 0x0C404
|
||||
#define HDMI_CORE_AUD_INT 0x0C408
|
||||
#define HDMI_CORE_AUD_N1 0x0C800
|
||||
#define HDMI_CORE_AUD_N2 0x0C804
|
||||
#define HDMI_CORE_AUD_N3 0x0C808
|
||||
#define HDMI_CORE_AUD_CTS1 0x0C80C
|
||||
#define HDMI_CORE_AUD_CTS2 0x0C810
|
||||
#define HDMI_CORE_AUD_CTS3 0x0C814
|
||||
#define HDMI_CORE_AUD_INCLKFS 0x0C818
|
||||
#define HDMI_CORE_AUD_CC08 0x0CC08
|
||||
#define HDMI_CORE_AUD_GP_CONF0 0x0D400
|
||||
#define HDMI_CORE_AUD_GP_CONF1 0x0D404
|
||||
#define HDMI_CORE_AUD_GP_CONF2 0x0D408
|
||||
#define HDMI_CORE_AUD_D010 0x0D010
|
||||
#define HDMI_CORE_AUD_GP_STAT 0x0D40C
|
||||
#define HDMI_CORE_AUD_GP_INT 0x0D410
|
||||
#define HDMI_CORE_AUD_GP_POL 0x0D414
|
||||
#define HDMI_CORE_AUD_GP_MASK 0x0D418
|
||||
|
||||
/* HDMI Main Controller */
|
||||
#define HDMI_CORE_MC_CLKDIS 0x10004
|
||||
#define HDMI_CORE_MC_SWRSTZREQ 0x10008
|
||||
#define HDMI_CORE_MC_FLOWCTRL 0x10010
|
||||
#define HDMI_CORE_MC_PHYRSTZ 0x10014
|
||||
#define HDMI_CORE_MC_LOCKONCLOCK 0x10018
|
||||
|
||||
/* HDMI COLOR SPACE CONVERTER */
|
||||
#define HDMI_CORE_CSC_CFG 0x10400
|
||||
#define HDMI_CORE_CSC_SCALE 0x10404
|
||||
#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408
|
||||
#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C
|
||||
#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410
|
||||
#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414
|
||||
#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418
|
||||
#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C
|
||||
#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420
|
||||
#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424
|
||||
#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428
|
||||
#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C
|
||||
#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430
|
||||
#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434
|
||||
#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438
|
||||
#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C
|
||||
#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440
|
||||
#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444
|
||||
#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448
|
||||
#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C
|
||||
#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450
|
||||
#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454
|
||||
#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458
|
||||
#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C
|
||||
#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460
|
||||
#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464
|
||||
|
||||
/* HDMI HDCP */
|
||||
#define HDMI_CORE_HDCP_MASK 0x14020
|
||||
|
||||
/* HDMI CEC */
|
||||
#define HDMI_CORE_CEC_MASK 0x17408
|
||||
|
||||
/* HDMI I2C Master */
|
||||
#define HDMI_CORE_I2CM_SLAVE 0x157C8
|
||||
#define HDMI_CORE_I2CM_ADDRESS 0x157CC
|
||||
#define HDMI_CORE_I2CM_DATAO 0x157D0
|
||||
#define HDMI_CORE_I2CM_DATAI 0X157D4
|
||||
#define HDMI_CORE_I2CM_OPERATION 0x157D8
|
||||
#define HDMI_CORE_I2CM_INT 0x157DC
|
||||
#define HDMI_CORE_I2CM_CTLINT 0x157E0
|
||||
#define HDMI_CORE_I2CM_DIV 0x157E4
|
||||
#define HDMI_CORE_I2CM_SEGADDR 0x157E8
|
||||
#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC
|
||||
#define HDMI_CORE_I2CM_SEGPTR 0x157F0
|
||||
#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4
|
||||
#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8
|
||||
#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC
|
||||
#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800
|
||||
#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804
|
||||
#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808
|
||||
#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C
|
||||
#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810
|
||||
#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814
|
||||
|
||||
enum hdmi_core_packet_mode {
|
||||
HDMI_PACKETMODERESERVEDVALUE = 0,
|
||||
HDMI_PACKETMODE24BITPERPIXEL = 4,
|
||||
HDMI_PACKETMODE30BITPERPIXEL = 5,
|
||||
HDMI_PACKETMODE36BITPERPIXEL = 6,
|
||||
HDMI_PACKETMODE48BITPERPIXEL = 7,
|
||||
};
|
||||
|
||||
struct hdmi_core_vid_config {
|
||||
struct hdmi_config v_fc_config;
|
||||
enum hdmi_core_packet_mode packet_mode;
|
||||
int data_enable_pol;
|
||||
int vblank_osc;
|
||||
int hblank;
|
||||
int vblank;
|
||||
};
|
||||
|
||||
struct csc_table {
|
||||
u16 a1, a2, a3, a4;
|
||||
u16 b1, b2, b3, b4;
|
||||
u16 c1, c2, c3, c4;
|
||||
};
|
||||
|
||||
int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len);
|
||||
void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s);
|
||||
int hdmi5_core_handle_irqs(struct hdmi_core_data *core);
|
||||
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||
struct hdmi_config *cfg);
|
||||
int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
|
||||
|
||||
#if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
|
||||
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
|
||||
struct omap_dss_audio *audio, u32 pclk);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -185,7 +185,7 @@ void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
|
|||
timings->interlace = param->timings.interlace;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
|
||||
#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
|
||||
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
|
||||
struct hdmi_audio_format *aud_fmt)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue