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drm/radeon/dpm: fix r600_enable_sclk_control() 

Actually program the correct register to enable
engine clock scaling control.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Alex Deucher 2013-07-25 21:46:21 -04:00
parent f4f85a8c94
commit f5d9b7f0f9
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/radeon/r600_dpm.c
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@ -278,9 +278,9 @@ bool r600_dynamicpm_enabled(struct radeon_device *rdev)
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
{
if (enable)
WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
else
WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
}
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)