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usb: dwc2: Speed dwc2_get_hwparams() on some host-only ports 

On some host-only DWC2 ports (like the one in rk3288) when we set
GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the
bit set.  Presumably that's because the port is always forced to HOST
mode so there's no reason to implement these status bits.

Since we know dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
hifive-unleashed-5.1
Douglas Anderson 2015-12-17 11:14:54 -08:00 committed by Felipe Balbi
parent 0fe239bc19
commit f619473140
1 changed files with 4 additions and 4 deletions
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8
drivers/usb/dwc2/core.c
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@ -3102,7 +3102,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
unsigned width;
u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
u32 hptxfsiz, grxfsiz, gnptxfsiz;
u32 gusbcfg;
u32 gusbcfg = 0;
/*
* Attempt to ensure this device is really a DWC_otg Controller.
@ -3135,8 +3135,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
if (hsotg->dr_mode != USB_DR_MODE_HOST) {
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
hsotg->regs + GUSBCFG);
usleep_range(100000, 150000);
@ -3146,7 +3146,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
if (!(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
if (hsotg->dr_mode != USB_DR_MODE_HOST) {
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
usleep_range(100000, 150000);
}