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ARM: dts: imx6ul: segin: Move ECSPI interface to board include file 

The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
alistair/sunxi64-5.4-dsi
Stefan Riedmueller 2019-07-09 09:19:25 +02:00 committed by Shawn Guo
parent b349580a4c
commit f638e7fdbf
2 changed files with 16 additions and 14 deletions
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14
arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
View File

@ -28,9 +28,6 @@
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -93,14 +90,3 @@
&usdhc1 {
status = "okay";
};
&iomuxc {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>;
};
};

16
arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
View File

@ -103,6 +103,13 @@
assigned-clock-rates = <786432000>;
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@ -225,6 +232,15 @@
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0