Altera TSE: Add Altera Ethernet Driver SGDMA file components
This patch adds the SGDMA soft IP support for the Altera Triple Speed Ethernet driver. Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Vince Bridgers
David S. Miller
parent
94fb0ef4dc
commit
f64f8808bc
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@ -0,0 +1,511 @@
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/* Altera TSE SGDMA and MSGDMA Linux driver
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* Copyright (C) 2014 Altera Corporation. All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/list.h>
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#include "altera_utils.h"
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#include "altera_tse.h"
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#include "altera_sgdmahw.h"
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#include "altera_sgdma.h"
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static void sgdma_descrip(struct sgdma_descrip *desc,
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struct sgdma_descrip *ndesc,
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dma_addr_t ndesc_phys,
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dma_addr_t raddr,
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dma_addr_t waddr,
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u16 length,
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int generate_eop,
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int rfixed,
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int wfixed);
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static int sgdma_async_write(struct altera_tse_private *priv,
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struct sgdma_descrip *desc);
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static int sgdma_async_read(struct altera_tse_private *priv);
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static dma_addr_t
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sgdma_txphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip *desc);
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static dma_addr_t
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sgdma_rxphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip *desc);
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static int sgdma_txbusy(struct altera_tse_private *priv);
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static int sgdma_rxbusy(struct altera_tse_private *priv);
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static void
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queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer);
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static void
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queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer);
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static struct tse_buffer *
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dequeue_tx(struct altera_tse_private *priv);
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static struct tse_buffer *
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dequeue_rx(struct altera_tse_private *priv);
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static struct tse_buffer *
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queue_rx_peekhead(struct altera_tse_private *priv);
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int sgdma_initialize(struct altera_tse_private *priv)
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{
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priv->txctrlreg = SGDMA_CTRLREG_ILASTD;
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priv->rxctrlreg = SGDMA_CTRLREG_IDESCRIP |
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SGDMA_CTRLREG_ILASTD;
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INIT_LIST_HEAD(&priv->txlisthd);
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INIT_LIST_HEAD(&priv->rxlisthd);
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priv->rxdescphys = (dma_addr_t) 0;
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priv->txdescphys = (dma_addr_t) 0;
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priv->rxdescphys = dma_map_single(priv->device, priv->rx_dma_desc,
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priv->rxdescmem, DMA_BIDIRECTIONAL);
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if (dma_mapping_error(priv->device, priv->rxdescphys)) {
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sgdma_uninitialize(priv);
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netdev_err(priv->dev, "error mapping rx descriptor memory\n");
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return -EINVAL;
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}
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priv->txdescphys = dma_map_single(priv->device, priv->rx_dma_desc,
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priv->rxdescmem, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->device, priv->txdescphys)) {
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sgdma_uninitialize(priv);
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netdev_err(priv->dev, "error mapping tx descriptor memory\n");
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return -EINVAL;
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}
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return 0;
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}
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void sgdma_uninitialize(struct altera_tse_private *priv)
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{
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if (priv->rxdescphys)
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dma_unmap_single(priv->device, priv->rxdescphys,
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priv->rxdescmem, DMA_BIDIRECTIONAL);
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if (priv->txdescphys)
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dma_unmap_single(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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}
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/* This function resets the SGDMA controller and clears the
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* descriptor memory used for transmits and receives.
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*/
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void sgdma_reset(struct altera_tse_private *priv)
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{
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u32 *ptxdescripmem = (u32 *)priv->tx_dma_desc;
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u32 txdescriplen = priv->txdescmem;
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u32 *prxdescripmem = (u32 *)priv->rx_dma_desc;
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u32 rxdescriplen = priv->rxdescmem;
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struct sgdma_csr *ptxsgdma = (struct sgdma_csr *)priv->tx_dma_csr;
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struct sgdma_csr *prxsgdma = (struct sgdma_csr *)priv->rx_dma_csr;
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/* Initialize descriptor memory to 0 */
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memset(ptxdescripmem, 0, txdescriplen);
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memset(prxdescripmem, 0, rxdescriplen);
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iowrite32(SGDMA_CTRLREG_RESET, &ptxsgdma->control);
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iowrite32(0, &ptxsgdma->control);
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iowrite32(SGDMA_CTRLREG_RESET, &prxsgdma->control);
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iowrite32(0, &prxsgdma->control);
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}
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void sgdma_enable_rxirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
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priv->rxctrlreg |= SGDMA_CTRLREG_INTEN;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_INTEN);
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}
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void sgdma_enable_txirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
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priv->txctrlreg |= SGDMA_CTRLREG_INTEN;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_INTEN);
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}
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/* for SGDMA, RX interrupts remain enabled after enabling */
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void sgdma_disable_rxirq(struct altera_tse_private *priv)
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{
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}
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/* for SGDMA, TX interrupts remain enabled after enabling */
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void sgdma_disable_txirq(struct altera_tse_private *priv)
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{
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}
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void sgdma_clear_rxirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
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}
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void sgdma_clear_txirq(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
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tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT);
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}
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/* transmits buffer through SGDMA. Returns number of buffers
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* transmitted, 0 if not possible.
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*
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* tx_lock is held by the caller
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*/
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int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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int pktstx = 0;
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struct sgdma_descrip *descbase =
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(struct sgdma_descrip *)priv->tx_dma_desc;
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struct sgdma_descrip *cdesc = &descbase[0];
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struct sgdma_descrip *ndesc = &descbase[1];
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/* wait 'til the tx sgdma is ready for the next transmit request */
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if (sgdma_txbusy(priv))
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return 0;
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sgdma_descrip(cdesc, /* current descriptor */
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ndesc, /* next descriptor */
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sgdma_txphysaddr(priv, ndesc),
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buffer->dma_addr, /* address of packet to xmit */
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0, /* write addr 0 for tx dma */
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buffer->len, /* length of packet */
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SGDMA_CONTROL_EOP, /* Generate EOP */
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0, /* read fixed */
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SGDMA_CONTROL_WR_FIXED); /* Generate SOP */
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pktstx = sgdma_async_write(priv, cdesc);
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/* enqueue the request to the pending transmit queue */
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queue_tx(priv, buffer);
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return 1;
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}
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/* tx_lock held to protect access to queued tx list
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*/
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u32 sgdma_tx_completions(struct altera_tse_private *priv)
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{
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u32 ready = 0;
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struct sgdma_descrip *desc = (struct sgdma_descrip *)priv->tx_dma_desc;
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if (!sgdma_txbusy(priv) &&
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((desc->control & SGDMA_CONTROL_HW_OWNED) == 0) &&
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(dequeue_tx(priv))) {
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ready = 1;
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}
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return ready;
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}
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int sgdma_add_rx_desc(struct altera_tse_private *priv,
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struct tse_buffer *rxbuffer)
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{
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queue_rx(priv, rxbuffer);
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return sgdma_async_read(priv);
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}
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/* status is returned on upper 16 bits,
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* length is returned in lower 16 bits
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*/
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u32 sgdma_rx_status(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
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struct sgdma_descrip *base = (struct sgdma_descrip *)priv->rx_dma_desc;
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struct sgdma_descrip *desc = NULL;
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int pktsrx;
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unsigned int rxstatus = 0;
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unsigned int pktlength = 0;
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unsigned int pktstatus = 0;
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struct tse_buffer *rxbuffer = NULL;
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dma_sync_single_for_cpu(priv->device,
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priv->rxdescphys,
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priv->rxdescmem,
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DMA_BIDIRECTIONAL);
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desc = &base[0];
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if ((ioread32(&csr->status) & SGDMA_STSREG_EOP) ||
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(desc->status & SGDMA_STATUS_EOP)) {
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pktlength = desc->bytes_xferred;
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pktstatus = desc->status & 0x3f;
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rxstatus = pktstatus;
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rxstatus = rxstatus << 16;
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rxstatus |= (pktlength & 0xffff);
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desc->status = 0;
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rxbuffer = dequeue_rx(priv);
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if (rxbuffer == NULL)
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netdev_err(priv->dev,
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"sgdma rx and rx queue empty!\n");
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/* kick the rx sgdma after reaping this descriptor */
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pktsrx = sgdma_async_read(priv);
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}
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return rxstatus;
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}
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/* Private functions */
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static void sgdma_descrip(struct sgdma_descrip *desc,
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struct sgdma_descrip *ndesc,
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dma_addr_t ndesc_phys,
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dma_addr_t raddr,
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dma_addr_t waddr,
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u16 length,
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int generate_eop,
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int rfixed,
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int wfixed)
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{
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/* Clear the next descriptor as not owned by hardware */
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u32 ctrl = ndesc->control;
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ctrl &= ~SGDMA_CONTROL_HW_OWNED;
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ndesc->control = ctrl;
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ctrl = 0;
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ctrl = SGDMA_CONTROL_HW_OWNED;
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ctrl |= generate_eop;
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ctrl |= rfixed;
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ctrl |= wfixed;
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/* Channel is implicitly zero, initialized to 0 by default */
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desc->raddr = raddr;
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desc->waddr = waddr;
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desc->next = lower_32_bits(ndesc_phys);
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desc->control = ctrl;
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desc->status = 0;
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desc->rburst = 0;
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desc->wburst = 0;
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desc->bytes = length;
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desc->bytes_xferred = 0;
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}
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/* If hardware is busy, don't restart async read.
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* if status register is 0 - meaning initial state, restart async read,
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* probably for the first time when populating a receive buffer.
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* If read status indicate not busy and a status, restart the async
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* DMA read.
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*/
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static int sgdma_async_read(struct altera_tse_private *priv)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
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struct sgdma_descrip *descbase =
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(struct sgdma_descrip *)priv->rx_dma_desc;
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struct sgdma_descrip *cdesc = &descbase[0];
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struct sgdma_descrip *ndesc = &descbase[1];
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unsigned int sts = ioread32(&csr->status);
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struct tse_buffer *rxbuffer = NULL;
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if (!sgdma_rxbusy(priv)) {
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rxbuffer = queue_rx_peekhead(priv);
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if (rxbuffer == NULL)
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return 0;
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sgdma_descrip(cdesc, /* current descriptor */
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ndesc, /* next descriptor */
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sgdma_rxphysaddr(priv, ndesc),
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0, /* read addr 0 for rx dma */
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rxbuffer->dma_addr, /* write addr for rx dma */
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0, /* read 'til EOP */
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0, /* EOP: NA for rx dma */
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0, /* read fixed: NA for rx dma */
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0); /* SOP: NA for rx DMA */
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/* clear control and status */
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iowrite32(0, &csr->control);
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/* If statuc available, clear those bits */
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if (sts & 0xf)
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iowrite32(0xf, &csr->status);
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dma_sync_single_for_device(priv->device,
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priv->rxdescphys,
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priv->rxdescmem,
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DMA_BIDIRECTIONAL);
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iowrite32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
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&csr->next_descrip);
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iowrite32((priv->rxctrlreg | SGDMA_CTRLREG_START),
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&csr->control);
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return 1;
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}
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return 0;
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}
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static int sgdma_async_write(struct altera_tse_private *priv,
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struct sgdma_descrip *desc)
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{
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struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
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if (sgdma_txbusy(priv))
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return 0;
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/* clear control and status */
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iowrite32(0, &csr->control);
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iowrite32(0x1f, &csr->status);
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dma_sync_single_for_device(priv->device, priv->txdescphys,
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priv->txdescmem, DMA_TO_DEVICE);
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iowrite32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
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&csr->next_descrip);
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iowrite32((priv->txctrlreg | SGDMA_CTRLREG_START),
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&csr->control);
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return 1;
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}
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static dma_addr_t
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sgdma_txphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip *desc)
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{
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dma_addr_t paddr = priv->txdescmem_busaddr;
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dma_addr_t offs = (dma_addr_t)((dma_addr_t)desc -
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(dma_addr_t)priv->tx_dma_desc);
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return paddr + offs;
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}
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static dma_addr_t
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sgdma_rxphysaddr(struct altera_tse_private *priv,
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struct sgdma_descrip *desc)
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{
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dma_addr_t paddr = priv->rxdescmem_busaddr;
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dma_addr_t offs = (dma_addr_t)((dma_addr_t)desc -
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(dma_addr_t)priv->rx_dma_desc);
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return paddr + offs;
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}
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#define list_remove_head(list, entry, type, member) \
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do { \
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entry = NULL; \
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if (!list_empty(list)) { \
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entry = list_entry((list)->next, type, member); \
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list_del_init(&entry->member); \
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} \
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} while (0)
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#define list_peek_head(list, entry, type, member) \
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do { \
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entry = NULL; \
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if (!list_empty(list)) { \
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entry = list_entry((list)->next, type, member); \
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} \
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} while (0)
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/* adds a tse_buffer to the tail of a tx buffer list.
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static void
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queue_tx(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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list_add_tail(&buffer->lh, &priv->txlisthd);
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}
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/* adds a tse_buffer to the tail of a rx buffer list
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static void
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queue_rx(struct altera_tse_private *priv, struct tse_buffer *buffer)
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{
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list_add_tail(&buffer->lh, &priv->rxlisthd);
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}
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/* dequeues a tse_buffer from the transmit buffer list, otherwise
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* returns NULL if empty.
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static struct tse_buffer *
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dequeue_tx(struct altera_tse_private *priv)
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{
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struct tse_buffer *buffer = NULL;
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list_remove_head(&priv->txlisthd, buffer, struct tse_buffer, lh);
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return buffer;
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}
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/* dequeues a tse_buffer from the receive buffer list, otherwise
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* returns NULL if empty
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* assumes the caller is managing and holding a mutual exclusion
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* primitive to avoid simultaneous pushes/pops to the list.
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*/
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static struct tse_buffer *
|
||||
dequeue_rx(struct altera_tse_private *priv)
|
||||
{
|
||||
struct tse_buffer *buffer = NULL;
|
||||
list_remove_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
|
||||
return buffer;
|
||||
}
|
||||
|
||||
/* dequeues a tse_buffer from the receive buffer list, otherwise
|
||||
* returns NULL if empty
|
||||
* assumes the caller is managing and holding a mutual exclusion
|
||||
* primitive to avoid simultaneous pushes/pops to the list while the
|
||||
* head is being examined.
|
||||
*/
|
||||
static struct tse_buffer *
|
||||
queue_rx_peekhead(struct altera_tse_private *priv)
|
||||
{
|
||||
struct tse_buffer *buffer = NULL;
|
||||
list_peek_head(&priv->rxlisthd, buffer, struct tse_buffer, lh);
|
||||
return buffer;
|
||||
}
|
||||
|
||||
/* check and return rx sgdma status without polling
|
||||
*/
|
||||
static int sgdma_rxbusy(struct altera_tse_private *priv)
|
||||
{
|
||||
struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr;
|
||||
return ioread32(&csr->status) & SGDMA_STSREG_BUSY;
|
||||
}
|
||||
|
||||
/* waits for the tx sgdma to finish it's current operation, returns 0
|
||||
* when it transitions to nonbusy, returns 1 if the operation times out
|
||||
*/
|
||||
static int sgdma_txbusy(struct altera_tse_private *priv)
|
||||
{
|
||||
int delay = 0;
|
||||
struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
|
||||
|
||||
/* if DMA is busy, wait for current transactino to finish */
|
||||
while ((ioread32(&csr->status) & SGDMA_STSREG_BUSY) && (delay++ < 100))
|
||||
udelay(1);
|
||||
|
||||
if (ioread32(&csr->status) & SGDMA_STSREG_BUSY) {
|
||||
netdev_err(priv->dev, "timeout waiting for tx dma\n");
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* Altera TSE SGDMA and MSGDMA Linux driver
|
||||
* Copyright (C) 2014 Altera Corporation. All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __ALTERA_SGDMA_H__
|
||||
#define __ALTERA_SGDMA_H__
|
||||
|
||||
void sgdma_reset(struct altera_tse_private *);
|
||||
void sgdma_enable_txirq(struct altera_tse_private *);
|
||||
void sgdma_enable_rxirq(struct altera_tse_private *);
|
||||
void sgdma_disable_rxirq(struct altera_tse_private *);
|
||||
void sgdma_disable_txirq(struct altera_tse_private *);
|
||||
void sgdma_clear_rxirq(struct altera_tse_private *);
|
||||
void sgdma_clear_txirq(struct altera_tse_private *);
|
||||
int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *);
|
||||
u32 sgdma_tx_completions(struct altera_tse_private *);
|
||||
int sgdma_add_rx_desc(struct altera_tse_private *priv, struct tse_buffer *);
|
||||
void sgdma_status(struct altera_tse_private *);
|
||||
u32 sgdma_rx_status(struct altera_tse_private *);
|
||||
int sgdma_initialize(struct altera_tse_private *);
|
||||
void sgdma_uninitialize(struct altera_tse_private *);
|
||||
|
||||
#endif /* __ALTERA_SGDMA_H__ */
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/* Altera TSE SGDMA and MSGDMA Linux driver
|
||||
* Copyright (C) 2014 Altera Corporation. All rights reserved
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __ALTERA_SGDMAHW_H__
|
||||
#define __ALTERA_SGDMAHW_H__
|
||||
|
||||
/* SGDMA descriptor structure */
|
||||
struct sgdma_descrip {
|
||||
unsigned int raddr; /* address of data to be read */
|
||||
unsigned int pad1;
|
||||
unsigned int waddr;
|
||||
unsigned int pad2;
|
||||
unsigned int next;
|
||||
unsigned int pad3;
|
||||
unsigned short bytes;
|
||||
unsigned char rburst;
|
||||
unsigned char wburst;
|
||||
unsigned short bytes_xferred; /* 16 bits, bytes xferred */
|
||||
|
||||
/* bit 0: error
|
||||
* bit 1: length error
|
||||
* bit 2: crc error
|
||||
* bit 3: truncated error
|
||||
* bit 4: phy error
|
||||
* bit 5: collision error
|
||||
* bit 6: reserved
|
||||
* bit 7: status eop for recv case
|
||||
*/
|
||||
unsigned char status;
|
||||
|
||||
/* bit 0: eop
|
||||
* bit 1: read_fixed
|
||||
* bit 2: write fixed
|
||||
* bits 3,4,5,6: Channel (always 0)
|
||||
* bit 7: hardware owned
|
||||
*/
|
||||
unsigned char control;
|
||||
} __packed;
|
||||
|
||||
|
||||
#define SGDMA_STATUS_ERR BIT(0)
|
||||
#define SGDMA_STATUS_LENGTH_ERR BIT(1)
|
||||
#define SGDMA_STATUS_CRC_ERR BIT(2)
|
||||
#define SGDMA_STATUS_TRUNC_ERR BIT(3)
|
||||
#define SGDMA_STATUS_PHY_ERR BIT(4)
|
||||
#define SGDMA_STATUS_COLL_ERR BIT(5)
|
||||
#define SGDMA_STATUS_EOP BIT(7)
|
||||
|
||||
#define SGDMA_CONTROL_EOP BIT(0)
|
||||
#define SGDMA_CONTROL_RD_FIXED BIT(1)
|
||||
#define SGDMA_CONTROL_WR_FIXED BIT(2)
|
||||
|
||||
/* Channel is always 0, so just zero initialize it */
|
||||
|
||||
#define SGDMA_CONTROL_HW_OWNED BIT(7)
|
||||
|
||||
/* SGDMA register space */
|
||||
struct sgdma_csr {
|
||||
/* bit 0: error
|
||||
* bit 1: eop
|
||||
* bit 2: descriptor completed
|
||||
* bit 3: chain completed
|
||||
* bit 4: busy
|
||||
* remainder reserved
|
||||
*/
|
||||
u32 status;
|
||||
u32 pad1[3];
|
||||
|
||||
/* bit 0: interrupt on error
|
||||
* bit 1: interrupt on eop
|
||||
* bit 2: interrupt after every descriptor
|
||||
* bit 3: interrupt after last descrip in a chain
|
||||
* bit 4: global interrupt enable
|
||||
* bit 5: starts descriptor processing
|
||||
* bit 6: stop core on dma error
|
||||
* bit 7: interrupt on max descriptors
|
||||
* bits 8-15: max descriptors to generate interrupt
|
||||
* bit 16: Software reset
|
||||
* bit 17: clears owned by hardware if 0, does not clear otherwise
|
||||
* bit 18: enables descriptor polling mode
|
||||
* bit 19-26: clocks before polling again
|
||||
* bit 27-30: reserved
|
||||
* bit 31: clear interrupt
|
||||
*/
|
||||
u32 control;
|
||||
u32 pad2[3];
|
||||
u32 next_descrip;
|
||||
u32 pad3[3];
|
||||
};
|
||||
|
||||
|
||||
#define SGDMA_STSREG_ERR BIT(0) /* Error */
|
||||
#define SGDMA_STSREG_EOP BIT(1) /* EOP */
|
||||
#define SGDMA_STSREG_DESCRIP BIT(2) /* Descriptor completed */
|
||||
#define SGDMA_STSREG_CHAIN BIT(3) /* Chain completed */
|
||||
#define SGDMA_STSREG_BUSY BIT(4) /* Controller busy */
|
||||
|
||||
#define SGDMA_CTRLREG_IOE BIT(0) /* Interrupt on error */
|
||||
#define SGDMA_CTRLREG_IOEOP BIT(1) /* Interrupt on EOP */
|
||||
#define SGDMA_CTRLREG_IDESCRIP BIT(2) /* Interrupt after every descriptor */
|
||||
#define SGDMA_CTRLREG_ILASTD BIT(3) /* Interrupt after last descriptor */
|
||||
#define SGDMA_CTRLREG_INTEN BIT(4) /* Global Interrupt enable */
|
||||
#define SGDMA_CTRLREG_START BIT(5) /* starts descriptor processing */
|
||||
#define SGDMA_CTRLREG_STOPERR BIT(6) /* stop on dma error */
|
||||
#define SGDMA_CTRLREG_INTMAX BIT(7) /* Interrupt on max descriptors */
|
||||
#define SGDMA_CTRLREG_RESET BIT(16)/* Software reset */
|
||||
#define SGDMA_CTRLREG_COBHW BIT(17)/* Clears owned by hardware */
|
||||
#define SGDMA_CTRLREG_POLL BIT(18)/* enables descriptor polling mode */
|
||||
#define SGDMA_CTRLREG_CLRINT BIT(31)/* Clears interrupt */
|
||||
|
||||
#endif /* __ALTERA_SGDMAHW_H__ */
|
||||
Loading…
Reference in New Issue