drm/radeon: Add support for RLC init on CIK (v4)
RLC handles the interrupt controller and other tasks on the GPU. v2: add documentation v3: update programming sequence v4: additional setup Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2777,3 +2777,145 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
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radeon_ring_write(ring, 0x0);
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}
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/*
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* RLC
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* The RLC is a multi-purpose microengine that handles a
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* variety of functions, the most important of which is
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* the interrupt controller.
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*/
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/**
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* cik_rlc_stop - stop the RLC ME
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*
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* @rdev: radeon_device pointer
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*
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* Halt the RLC ME (MicroEngine) (CIK).
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*/
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static void cik_rlc_stop(struct radeon_device *rdev)
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{
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int i, j, k;
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u32 mask, tmp;
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tmp = RREG32(CP_INT_CNTL_RING0);
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tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING0, tmp);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
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WREG32(RLC_CGCG_CGLS_CTRL, tmp);
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WREG32(RLC_CNTL, 0);
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for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
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for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
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cik_select_se_sh(rdev, i, j);
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for (k = 0; k < rdev->usec_timeout; k++) {
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if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
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break;
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udelay(1);
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}
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}
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}
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
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for (k = 0; k < rdev->usec_timeout; k++) {
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if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
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break;
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udelay(1);
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}
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}
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/**
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* cik_rlc_start - start the RLC ME
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*
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* @rdev: radeon_device pointer
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*
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* Unhalt the RLC ME (MicroEngine) (CIK).
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*/
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static void cik_rlc_start(struct radeon_device *rdev)
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{
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u32 tmp;
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WREG32(RLC_CNTL, RLC_ENABLE);
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tmp = RREG32(CP_INT_CNTL_RING0);
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tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
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WREG32(CP_INT_CNTL_RING0, tmp);
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udelay(50);
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}
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/**
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* cik_rlc_resume - setup the RLC hw
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*
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* @rdev: radeon_device pointer
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*
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* Initialize the RLC registers, load the ucode,
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* and start the RLC (CIK).
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* Returns 0 for success, -EINVAL if the ucode is not available.
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*/
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static int cik_rlc_resume(struct radeon_device *rdev)
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{
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u32 i, size;
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u32 clear_state_info[3];
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const __be32 *fw_data;
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if (!rdev->rlc_fw)
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return -EINVAL;
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switch (rdev->family) {
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case CHIP_BONAIRE:
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default:
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size = BONAIRE_RLC_UCODE_SIZE;
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break;
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case CHIP_KAVERI:
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size = KV_RLC_UCODE_SIZE;
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break;
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case CHIP_KABINI:
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size = KB_RLC_UCODE_SIZE;
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break;
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}
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cik_rlc_stop(rdev);
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WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC);
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RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(RLC_LB_CNTR_INIT, 0);
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WREG32(RLC_LB_CNTR_MAX, 0x00008000);
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cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
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WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
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WREG32(RLC_LB_PARAMS, 0x00600408);
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WREG32(RLC_LB_CNTL, 0x80000004);
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WREG32(RLC_MC_CNTL, 0);
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WREG32(RLC_UCODE_CNTL, 0);
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fw_data = (const __be32 *)rdev->rlc_fw->data;
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WREG32(RLC_GPM_UCODE_ADDR, 0);
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for (i = 0; i < size; i++)
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WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
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WREG32(RLC_GPM_UCODE_ADDR, 0);
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/* XXX */
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clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
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clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
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clear_state_info[2] = 0;//cik_default_size;
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WREG32(RLC_GPM_SCRATCH_ADDR, 0x3d);
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for (i = 0; i < 3; i++)
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WREG32(RLC_GPM_SCRATCH_DATA, clear_state_info[i]);
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WREG32(RLC_DRIVER_DMA_STATUS, 0);
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cik_rlc_start(rdev);
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return 0;
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}
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@ -497,10 +497,55 @@
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#define CP_MEC_ME2_UCODE_ADDR 0xC178
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#define CP_MEC_ME2_UCODE_DATA 0xC17C
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#define CP_INT_CNTL_RING0 0xC1A8
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# define CNTX_BUSY_INT_ENABLE (1 << 19)
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# define CNTX_EMPTY_INT_ENABLE (1 << 20)
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# define PRIV_INSTR_INT_ENABLE (1 << 22)
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# define PRIV_REG_INT_ENABLE (1 << 23)
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# define TIME_STAMP_INT_ENABLE (1 << 26)
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# define CP_RINGID2_INT_ENABLE (1 << 29)
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# define CP_RINGID1_INT_ENABLE (1 << 30)
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# define CP_RINGID0_INT_ENABLE (1 << 31)
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#define CP_MAX_CONTEXT 0xC2B8
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#define CP_RB0_BASE_HI 0xC2C4
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#define RLC_CNTL 0xC300
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# define RLC_ENABLE (1 << 0)
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#define RLC_MC_CNTL 0xC30C
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#define RLC_LB_CNTR_MAX 0xC348
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#define RLC_LB_CNTL 0xC364
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#define RLC_LB_CNTR_INIT 0xC36C
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#define RLC_SAVE_AND_RESTORE_BASE 0xC374
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#define RLC_DRIVER_DMA_STATUS 0xC378
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#define RLC_GPM_UCODE_ADDR 0xC388
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#define RLC_GPM_UCODE_DATA 0xC38C
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#define RLC_UCODE_CNTL 0xC39C
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#define RLC_CGCG_CGLS_CTRL 0xC424
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#define RLC_LB_INIT_CU_MASK 0xC43C
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#define RLC_LB_PARAMS 0xC444
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#define RLC_SERDES_CU_MASTER_BUSY 0xC484
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#define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
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# define SE_MASTER_BUSY_MASK 0x0000ffff
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# define GC_MASTER_BUSY (1 << 16)
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# define TC0_MASTER_BUSY (1 << 17)
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# define TC1_MASTER_BUSY (1 << 18)
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#define RLC_GPM_SCRATCH_ADDR 0xC4B0
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#define RLC_GPM_SCRATCH_DATA 0xC4B4
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#define PA_SC_RASTER_CONFIG 0x28350
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# define RASTER_CONFIG_RB_MAP_0 0
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# define RASTER_CONFIG_RB_MAP_1 1
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@ -599,6 +644,8 @@
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#define TCC_DISABLE_MASK 0xFFFF0000
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#define TCC_DISABLE_SHIFT 16
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#define CB_CGTT_SCLK_CTRL 0x3c2a0
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/*
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* PM4
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*/
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