drm/i915: Fix sandybridge status page setup.
The register's moved to the same location as the one for the BCS, it seems. Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -136,6 +136,12 @@ const static struct intel_device_info intel_ironlake_m_info = {
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.has_hotplug = 1,
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};
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const static struct intel_device_info intel_sandybridge_d_info = {
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.is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
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.has_pipe_cxsr = 1,
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.has_hotplug = 1,
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};
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const static struct pci_device_id pciidlist[] = {
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INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
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INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
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@ -167,6 +173,7 @@ const static struct pci_device_id pciidlist[] = {
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INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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{0, 0, 0}
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};
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@ -4581,8 +4581,13 @@ i915_gem_init_hws(struct drm_device *dev)
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}
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dev_priv->hws_obj = obj;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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if (IS_GEN6(dev)) {
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I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
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I915_READ(HWS_PGA_GEN6); /* posting read */
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} else {
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I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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I915_READ(HWS_PGA); /* posting read */
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}
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DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
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return 0;
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@ -269,6 +269,7 @@
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#define INSTDONE1 0x0207c /* 965+ only */
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#define ACTHD_I965 0x02074
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#define HWS_PGA 0x02080
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#define HWS_PGA_GEN6 0x04080
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#define HWS_ADDRESS_MASK 0xfffff000
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#define HWS_START_ADDRESS_SHIFT 4
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#define PWRCTXA 0x2088 /* 965GM+ only */
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