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Quite a bit of love for the rk3288-veyron chromeos devices and a number 

of cleanups for rk3288 from that area, hdmi support for the old rk3066
 a small rv1108-eglin-r1 cleanup and wifi+hdmi-cec for the tinker board.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlyjIKkQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgagZB/0djmLiIppQmphU5xz0nu9la/6qPpX2Mglk
 3XIi/pQXu+O/1i4aNJJwvk9k6cmX7nbVG2vQlLcsM/XNq0fy8Y4on9UThohkg23p
 Cf34w2pFn5Tp5bBTCWxa1LTi20UMVZsYZivy+/LdBlTIekEMNFHf6veIn8dBtnPW
 nFjDuvlhZqg6CaxVZ9Vn6xN1ClqleR0LuUcEt2X6wE8UocDs/01wZffcFbs3K0Uo
 mgz1vUd4DlhHJo2YlTa+T88OF13d7WXboNR67xJTlm69d0wfm+k3MFeZYAhiI4kx
 HdsqS+ZZxzsos7X3QCDiXMCbd070yGiDudD3UY4VCKymx9DzGWmp
 =YSCV
 -----END PGP SIGNATURE-----

Merge tag 'v5.2-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Quite a bit of love for the rk3288-veyron chromeos devices and a number
of cleanups for rk3288 from that area, hdmi support for the old rk3066
a small rv1108-eglin-r1 cleanup and wifi+hdmi-cec for the tinker board.

* tag 'v5.2-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: enable vop0 and hdmi nodes to rk3066a-mk808
  ARM: dts: rockchip: add rk3066 hdmi nodes
  ARM: dts: rockchip: Add device tree for rk3288-veyron-mighty
  dt-bindings: ARM: dts: rockchip: Add bindings for rk3288-veyron-mighty
  ARM: dts: rockchip: Add vdd_logic to rk3288-veyron
  ARM: dts: rockchip: Add dvs-gpios to rk3288-veyron-jerry
  ARM: dts: rockchip: Add rk3288-veyron-jerry rev 10-15
  dt-bindings: ARM: dts: rockchip: Add rk3288-veyron-jerry rev 10-15
  ARM: dts: rockchip: Fix gic/efuse sort ordering for rk3288
  ARM: dts: rockchip: Enable WiFi on rk3288-tinker
  ARM: dts: rockchip: add grf reference in rk3288 tsadc node
  ARM: dts: rockchip: Enable HDMI CEC on rk3288-tinker-s
  ARM: dts: rockchip: remove disable-wp from rv1108-elgin-r1 emmc node

Signed-off-by: Olof Johansson <olof@lixom.net>
hifive-unleashed-5.2
Olof Johansson 2019-04-28 12:15:24 -07:00
parent 1c93235a6d 4b028ebd4e
commit f6f9683c5a
11 changed files with 221 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -146,7 +146,7 @@ properties:
- const: google,gru
- const: rockchip,rk3399
- description: Google Jaq (Haier Chromebook 11 and more)
- description: Google Jaq (Haier Chromebook 11 and more w/ uSD)
items:
- const: google,veyron-jaq-rev5
- const: google,veyron-jaq-rev4
@ -159,6 +159,12 @@ properties:
- description: Google Jerry (Hisense Chromebook C11 and more)
items:
- const: google,veyron-jerry-rev15
- const: google,veyron-jerry-rev14
- const: google,veyron-jerry-rev13
- const: google,veyron-jerry-rev12
- const: google,veyron-jerry-rev11
- const: google,veyron-jerry-rev10
- const: google,veyron-jerry-rev7
- const: google,veyron-jerry-rev6
- const: google,veyron-jerry-rev5
@ -199,6 +205,17 @@ properties:
- const: google,veyron
- const: rockchip,rk3288
- description: Google Mighty (Haier Chromebook 11 and more w/ SD)
items:
- const: google,veyron-mighty-rev5
- const: google,veyron-mighty-rev4
- const: google,veyron-mighty-rev3
- const: google,veyron-mighty-rev2
- const: google,veyron-mighty-rev1
- const: google,veyron-mighty
- const: google,veyron
- const: rockchip,rk3288
- description: Google Minnie (Asus Chromebook Flip C100P)
items:
- const: google,veyron-minnie-rev4

1
arch/arm/boot/dts/Makefile
View File

@ -909,6 +909,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jaq.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-mighty.dtb \
rk3288-veyron-minnie.dtb \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb \

29
arch/arm/boot/dts/rk3066a-mk808.dts
View File

@ -30,6 +30,17 @@
};
};
hdmi_con {
compatible = "hdmi-connector";
type = "c";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vcc_io: vcc-io {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
@ -91,6 +102,20 @@
};
};
&hdmi {
status = "okay";
};
&hdmi_in_vop1 {
status = "disabled";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
@ -150,6 +175,10 @@
status = "okay";
};
&vop0 {
status = "okay";
};
&wdt {
status = "okay";
};

59
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -80,6 +80,11 @@
vop0_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop0_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop0>;
};
};
};
@ -101,6 +106,49 @@
vop1_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop1_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop1>;
};
};
};
hdmi: hdmi@10116000 {
compatible = "rockchip,rk3066-hdmi";
reg = <0x10116000 0x2000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HDMI>;
clock-names = "hclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
power-domains = <&power RK3066_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vop0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop0_out_hdmi>;
};
hdmi_in_vop1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vop1_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
@ -380,6 +428,17 @@
*/
};
hdmi {
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
};
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
<0 RK_PA2 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,

5
arch/arm/boot/dts/rk3288-tinker-s.dts
View File

@ -23,3 +23,8 @@
mmc-ddr-1_8v;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec_c0>;
};

37
arch/arm/boot/dts/rk3288-tinker.dtsi
View File

@ -5,6 +5,7 @@
#include "rk3288.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/clock/rockchip,rk808.h>
/ {
chosen {
@ -61,6 +62,16 @@
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 RK808_CLKOUT1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable>;
reset-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>,
<&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@ -337,6 +348,7 @@
status = "okay";
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;
};
&pinctrl {
@ -415,6 +427,13 @@
rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio {
wifi_enable: wifi-enable {
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
@ -439,6 +458,24 @@
vqmmc-supply = <&vccio_sd>;
};
&sdio0 {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <50000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc_18>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */

9
arch/arm/boot/dts/rk3288-veyron-jerry.dts
View File

@ -11,7 +11,10 @@
/ {
model = "Google Jerry";
compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
"google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
"google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
"google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
"google,veyron-jerry-rev3", "google,veyron-jerry",
"google,veyron", "rockchip,rk3288";
@ -61,7 +64,9 @@
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
<&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
regulators {
mic_vcc: LDO_REG2 {

34
arch/arm/boot/dts/rk3288-veyron-mighty.dts 100644
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron Mighty Rev 1+ board device tree source
*
* Copyright 2015 Google, Inc
*/
/dts-v1/;
#include "rk3288-veyron-jaq.dts"
/ {
model = "Google Mighty";
compatible = "google,veyron-mighty-rev5", "google,veyron-mighty-rev4",
"google,veyron-mighty-rev3", "google,veyron-mighty-rev2",
"google,veyron-mighty-rev1", "google,veyron-mighty",
"google,veyron", "rockchip,rk3288";
};
&sdmmc {
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
&sdmmc_wp_gpio &sdmmc_bus4>;
wp-gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>;
/delete-property/ disable-wp;
};
&pinctrl {
sdmmc {
sdmmc_wp_gpio: sdmmc-wp-gpio {
rockchip,pins = <7 10 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

17
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -95,6 +95,23 @@
regulator-boot-on;
vin-supply = <&vcc_5v>;
};
vdd_logic: vdd-logic {
compatible = "pwm-regulator";
regulator-name = "vdd_logic";
pwms = <&pwm1 0 1994 0>;
pwm-supply = <&vcc33_sys>;
pwm-dutycycle-range = <0x7b 0>;
pwm-dutycycle-unit = <0x94>;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <4000>;
};
};
&cpu0 {

27
arch/arm/boot/dts/rk3288.dtsi
View File

@ -569,6 +569,7 @@
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <1>;
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@ -1378,19 +1379,6 @@
reg = <0x0 0xffaf0080 0x0 0x20>;
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x0 0xffc01000 0x0 0x1000>,
<0x0 0xffc02000 0x0 0x2000>,
<0x0 0xffc04000 0x0 0x2000>,
<0x0 0xffc06000 0x0 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
reg = <0x0 0xffb40000 0x0 0x20>;
@ -1404,6 +1392,19 @@
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0x0 0xffc01000 0x0 0x1000>,
<0x0 0xffc02000 0x0 0x2000>,
<0x0 0xffc04000 0x0 0x2000>,
<0x0 0xffc06000 0x0 0x2000>;
interrupts = <GIC_PPI 9 0xf04>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3288-pinctrl";
rockchip,grf = <&grf>;

1
arch/arm/boot/dts/rv1108-elgin-r1.dts
View File

@ -37,7 +37,6 @@
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
no-sd;
no-sdio;
non-removable;