drm/radeon/kms: upstream power table updates
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -7270,6 +7270,8 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
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#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
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#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally
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#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
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#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16
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#define ATOM_PP_THERMALCONTROLLER_LM96163 17
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// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
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// We probably should reserve the bit 0x80 for this use.
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@ -7285,6 +7287,7 @@ typedef struct _ATOM_PPLIB_STATE
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UCHAR ucClockStateIndices[1]; // variable-sized
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} ATOM_PPLIB_STATE;
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typedef struct _ATOM_PPLIB_FANTABLE
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{
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UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same.
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@ -7297,12 +7300,20 @@ typedef struct _ATOM_PPLIB_FANTABLE
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USHORT usPWMHigh; // The PWM value at THigh.
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} ATOM_PPLIB_FANTABLE;
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typedef struct _ATOM_PPLIB_FANTABLE2
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{
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ATOM_PPLIB_FANTABLE basicTable;
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USHORT usTMax; // The max temperature
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} ATOM_PPLIB_FANTABLE2;
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typedef struct _ATOM_PPLIB_EXTENDEDHEADER
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{
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USHORT usSize;
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ULONG ulMaxEngineClock; // For Overdrive.
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ULONG ulMaxMemoryClock; // For Overdrive.
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// Add extra system parameters here, always adjust size to include all fields.
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USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
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USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
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} ATOM_PPLIB_EXTENDEDHEADER;
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//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
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@ -7325,6 +7336,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
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#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
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#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
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typedef struct _ATOM_PPLIB_POWERPLAYTABLE
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{
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ATOM_COMMON_TABLE_HEADER sHeader;
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@ -7383,7 +7395,8 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
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USHORT usVddciDependencyOnMCLKOffset;
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USHORT usVddcDependencyOnMCLKOffset;
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USHORT usMaxClockVoltageOnDCOffset;
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USHORT usReserved[2];
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USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
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USHORT usReserved;
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} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
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typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
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@ -7393,8 +7406,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
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ULONG ulNearTDPLimit;
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ULONG ulSQRampingThreshold;
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USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table
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ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed.
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ULONG ulReserved;
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ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table
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USHORT usTDPODLimit;
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USHORT usLoadLineSlope; // in milliOhms * 100
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} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
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//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
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@ -7423,6 +7437,7 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
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//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
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#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
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#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
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#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D)
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//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
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#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
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@ -7446,7 +7461,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
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#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
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#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
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#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
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#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
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#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
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//memory related flags
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@ -7508,7 +7525,7 @@ typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
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#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
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#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
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#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
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#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
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#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
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#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0).
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typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
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@ -7527,6 +7544,24 @@ typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
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} ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
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typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
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{
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USHORT usEngineClockLow;
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UCHAR ucEngineClockHigh;
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USHORT usMemoryClockLow;
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UCHAR ucMemoryClockHigh;
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USHORT usVDDC;
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USHORT usVDDCI;
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UCHAR ucPCIEGen;
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UCHAR ucUnused1;
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ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
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} ATOM_PPLIB_SI_CLOCK_INFO;
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typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
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{
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@ -7539,7 +7574,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
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UCHAR ucPadding; // For proper alignment and size.
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USHORT usVDDC; // For the 780, use: None, Low, High, Variable
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UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
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UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement.
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UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
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USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
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ULONG ulFlags;
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} ATOM_PPLIB_RS780_CLOCK_INFO;
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@ -7561,9 +7596,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
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USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
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UCHAR ucEngineClockHigh; //clockfrequency >> 16.
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UCHAR vddcIndex; //2-bit vddc index;
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UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value
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//please initalize to 0
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UCHAR rsv;
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USHORT tdpLimit;
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//please initalize to 0
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USHORT rsv1;
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//please initialize to 0s
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@ -7586,7 +7619,7 @@ typedef struct _ATOM_PPLIB_STATE_V2
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UCHAR clockInfoIndex[1];
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} ATOM_PPLIB_STATE_V2;
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typedef struct StateArray{
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typedef struct _StateArray{
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//how many states we have
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UCHAR ucNumEntries;
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@ -7594,18 +7627,17 @@ typedef struct StateArray{
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}StateArray;
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typedef struct ClockInfoArray{
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typedef struct _ClockInfoArray{
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//how many clock levels we have
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO)
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//sizeof(ATOM_PPLIB_CLOCK_INFO)
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UCHAR ucEntrySize;
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//this is for Sumo
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ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1];
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UCHAR clockInfo[1];
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}ClockInfoArray;
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typedef struct NonClockInfoArray{
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typedef struct _NonClockInfoArray{
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//how many non-clock levels we have. normally should be same as number of states
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UCHAR ucNumEntries;
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@ -7644,6 +7676,124 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
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ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
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}ATOM_PPLIB_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_CAC_Leakage_Record
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{
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USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations
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ULONG ulLeakageValue;
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}ATOM_PPLIB_CAC_Leakage_Record;
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typedef struct _ATOM_PPLIB_CAC_Leakage_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries.
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}ATOM_PPLIB_CAC_Leakage_Table;
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
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{
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USHORT usVoltage;
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USHORT usSclkLow;
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UCHAR ucSclkHigh;
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USHORT usMclkLow;
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UCHAR ucMclkHigh;
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}ATOM_PPLIB_PhaseSheddingLimits_Record;
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries.
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}ATOM_PPLIB_PhaseSheddingLimits_Table;
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typedef struct _VCEClockInfo{
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USHORT usEVClkLow;
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UCHAR ucEVClkHigh;
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USHORT usECClkLow;
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UCHAR ucECClkHigh;
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}VCEClockInfo;
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typedef struct _VCEClockInfoArray{
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UCHAR ucNumEntries;
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VCEClockInfo entries[1];
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}VCEClockInfoArray;
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
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{
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USHORT usVoltage;
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UCHAR ucVCEClockInfoIndex;
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}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record;
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
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}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_VCE_State_Record
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{
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UCHAR ucVCEClockInfoIndex;
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UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
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}ATOM_PPLIB_VCE_State_Record;
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typedef struct _ATOM_PPLIB_VCE_State_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_State_Record entries[1];
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}ATOM_PPLIB_VCE_State_Table;
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typedef struct _ATOM_PPLIB_VCE_Table
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{
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UCHAR revid;
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// VCEClockInfoArray array;
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// ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits;
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// ATOM_PPLIB_VCE_State_Table states;
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}ATOM_PPLIB_VCE_Table;
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typedef struct _UVDClockInfo{
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USHORT usVClkLow;
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UCHAR ucVClkHigh;
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USHORT usDClkLow;
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UCHAR ucDClkHigh;
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}UVDClockInfo;
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typedef struct _UVDClockInfoArray{
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UCHAR ucNumEntries;
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UVDClockInfo entries[1];
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}UVDClockInfoArray;
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
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{
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USHORT usVoltage;
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UCHAR ucUVDClockInfoIndex;
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}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record;
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
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}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_UVD_State_Record
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{
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UCHAR ucUVDClockInfoIndex;
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UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
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}ATOM_PPLIB_UVD_State_Record;
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typedef struct _ATOM_PPLIB_UVD_State_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_UVD_State_Record entries[1];
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}ATOM_PPLIB_UVD_State_Table;
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typedef struct _ATOM_PPLIB_UVD_Table
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{
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UCHAR revid;
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// UVDClockInfoArray array;
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// ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits;
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// ATOM_PPLIB_UVD_State_Table states;
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}ATOM_PPLIB_UVD_Table;
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/**************************************************************************/
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@ -2433,9 +2433,9 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
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int i, j, non_clock_array_index, clock_array_index;
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int state_index = 0, mode_index = 0;
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union pplib_clock_info *clock_info;
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struct StateArray *state_array;
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struct ClockInfoArray *clock_info_array;
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struct NonClockInfoArray *non_clock_info_array;
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struct _StateArray *state_array;
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struct _ClockInfoArray *clock_info_array;
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struct _NonClockInfoArray *non_clock_info_array;
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bool valid;
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union power_info *power_info;
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int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
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power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
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radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
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state_array = (struct StateArray *)
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state_array = (struct _StateArray *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib.usStateArrayOffset));
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clock_info_array = (struct ClockInfoArray *)
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clock_info_array = (struct _ClockInfoArray *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
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non_clock_info_array = (struct NonClockInfoArray *)
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non_clock_info_array = (struct _NonClockInfoArray *)
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(mode_info->atom_context->bios + data_offset +
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le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
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rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
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@ -2481,7 +2481,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
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if (clock_array_index >= clock_info_array->ucNumEntries)
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continue;
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clock_info = (union pplib_clock_info *)
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&clock_info_array->clockInfo[clock_array_index];
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&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
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valid = radeon_atombios_parse_pplib_clock_info(rdev,
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state_index, mode_index,
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clock_info);
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