mx25: add support for the CSI device
Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -139,6 +139,11 @@ static unsigned long get_rate_lcdc(struct clk *clk)
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return get_rate_per(7);
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}
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static unsigned long get_rate_csi(struct clk *clk)
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{
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return get_rate_per(0);
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}
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static unsigned long get_rate_otg(struct clk *clk)
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{
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unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
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@ -211,6 +216,8 @@ DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
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DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
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DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
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DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
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DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
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@ -232,6 +239,7 @@ DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
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DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
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DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
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DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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@ -269,6 +277,7 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
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_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
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_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
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_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
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_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
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};
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@ -284,8 +293,9 @@ int __init mx25_clocks_init(void)
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__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
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__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
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/* Clock source for lcdc is upll */
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__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
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/* Clock source for lcdc and csi is upll */
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__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
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CRM_BASE + 0x64);
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mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
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@ -571,3 +571,25 @@ struct platform_device imx_ssi_device1 = {
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.num_resources = ARRAY_SIZE(imx_ssi_resources1),
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.resource = imx_ssi_resources1,
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};
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static struct resource mx25_csi_resources[] = {
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{
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.start = MX25_CSI_BASE_ADDR,
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.end = MX25_CSI_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MX25_INT_CSI,
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.flags = IORESOURCE_IRQ
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},
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};
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struct platform_device mx25_csi_device = {
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.name = "mx2-camera",
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.id = 0,
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.num_resources = ARRAY_SIZE(mx25_csi_resources),
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.resource = mx25_csi_resources,
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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@ -25,3 +25,4 @@ extern struct platform_device mxc_wdt;
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extern struct platform_device mx25_kpp_device;
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extern struct platform_device imx_ssi_device0;
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extern struct platform_device imx_ssi_device1;
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extern struct platform_device mx25_csi_device;
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@ -39,9 +39,11 @@
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#define MX25_LCDC_BASE_ADDR 0x53fbc000
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#define MX25_KPP_BASE_ADDR 0x43fa8000
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#define MX25_OTG_BASE_ADDR 0x53ff4000
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#define MX25_CSI_BASE_ADDR 0x53ff8000
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#define MX25_INT_SSI2 11
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#define MX25_INT_SSI1 12
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#define MX25_INT_CSI 17
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#define MX25_INT_DRYICE 25
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#define MX25_INT_NANDFC 33
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#define MX25_INT_LCDC 39
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