Merge remote-tracking branch 'origin/spi/qspi' into spi/next
* origin/spi/qspi: spi: spi-fsl-qspi: Introduce variable to fix different invalid master Id dt-bindings: spi: spi-fsl-qspi: Add bindings of ls1088a and ls1012a spi: spi-fsl-qspi: dynamically alloc AHB memory for QSPI5.4-rM2-2.2.x-imx-squashed
commit
f7bb9c8545
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@ -6,6 +6,8 @@ Required properties:
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"fsl,ls1021a-qspi", "fsl,ls2080a-qspi"
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or
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"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
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"fsl,ls1012a-qspi" followed by "fsl,ls1021a-qspi"
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"fsl,ls1088a-qspi" followed by "fsl,ls2080a-qspi"
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- reg : the first contains the register location and length,
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the second contains the memory mapping address and length
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- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
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@ -63,6 +63,11 @@
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#define QUADSPI_IPCR 0x08
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#define QUADSPI_IPCR_SEQID(x) ((x) << 24)
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#define QUADSPI_BUF0CR 0x10
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#define QUADSPI_BUF1CR 0x14
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#define QUADSPI_BUF2CR 0x18
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#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
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#define QUADSPI_BUF3CR 0x1c
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#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31)
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#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8)
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@ -181,9 +186,12 @@
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*/
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#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4)
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#define QUADSPI_MIN_IOMAP SZ_4M
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struct fsl_qspi_devtype_data {
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unsigned int rxfifo;
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unsigned int txfifo;
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int invalid_mstrid;
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unsigned int ahb_buf_size;
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unsigned int quirks;
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bool little_endian;
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@ -192,6 +200,7 @@ struct fsl_qspi_devtype_data {
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static const struct fsl_qspi_devtype_data vybrid_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_64,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
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.little_endian = true,
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@ -200,6 +209,7 @@ static const struct fsl_qspi_devtype_data vybrid_data = {
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static const struct fsl_qspi_devtype_data imx6sx_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_512,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
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.little_endian = true,
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@ -208,6 +218,7 @@ static const struct fsl_qspi_devtype_data imx6sx_data = {
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static const struct fsl_qspi_devtype_data imx7d_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_512,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
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.little_endian = true,
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@ -216,6 +227,7 @@ static const struct fsl_qspi_devtype_data imx7d_data = {
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static const struct fsl_qspi_devtype_data imx6ul_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_512,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
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.little_endian = true,
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@ -224,6 +236,7 @@ static const struct fsl_qspi_devtype_data imx6ul_data = {
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static const struct fsl_qspi_devtype_data ls1021a_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_64,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = 0,
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.little_endian = false,
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@ -233,6 +246,7 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
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.rxfifo = SZ_128,
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.txfifo = SZ_64,
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.ahb_buf_size = SZ_1K,
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.invalid_mstrid = 0x0,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
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.little_endian = true,
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};
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@ -241,6 +255,9 @@ struct fsl_qspi {
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void __iomem *iobase;
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void __iomem *ahb_addr;
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u32 memmap_phy;
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u32 memmap_phy_size;
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u32 memmap_start;
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u32 memmap_len;
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struct clk *clk, *clk_en;
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struct device *dev;
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struct completion c;
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@ -519,11 +536,34 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
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fsl_qspi_invalidate(q);
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}
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static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
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static int fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
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{
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u32 start = op->addr.val + q->selected * q->memmap_phy_size / 4;
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u32 len = op->data.nbytes;
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/* if necessary, ioremap before AHB read */
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if ((!q->ahb_addr) || start < q->memmap_start ||
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start + len > q->memmap_start + q->memmap_len) {
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if (q->ahb_addr) {
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iounmap(q->ahb_addr);
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}
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q->memmap_start = start;
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q->memmap_len = len > QUADSPI_MIN_IOMAP ?
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len : QUADSPI_MIN_IOMAP;
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q->ahb_addr = ioremap_wc(q->memmap_phy + q->memmap_start,
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q->memmap_len);
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if (!q->ahb_addr) {
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dev_err(q->dev, "failed to alloc memory\n");
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return -ENOMEM;
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}
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}
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memcpy_fromio(op->data.buf.in,
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q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,
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op->data.nbytes);
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q->ahb_addr + start - q->memmap_start, len);
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return 0;
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}
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static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,
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@ -615,6 +655,7 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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void __iomem *base = q->iobase;
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u32 addr_offset = 0;
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int err = 0;
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int invalid_mstrid = q->devtype_data->invalid_mstrid;
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mutex_lock(&q->lock);
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@ -628,7 +669,7 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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addr_offset = q->memmap_phy;
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qspi_writel(q,
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q->selected * q->devtype_data->ahb_buf_size + addr_offset,
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q->selected * q->memmap_phy_size / 4 + addr_offset,
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base + QUADSPI_SFAR);
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qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
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@ -638,6 +679,10 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
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base + QUADSPI_SPTRCLR);
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qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
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qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
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qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
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fsl_qspi_prepare_lut(q, op);
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/*
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@ -647,7 +692,7 @@ static int fsl_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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*/
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if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&
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op->data.dir == SPI_MEM_DATA_IN) {
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fsl_qspi_read_ahb(q, op);
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err = fsl_qspi_read_ahb(q, op);
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} else {
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qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |
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QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
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@ -735,16 +780,16 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
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* In HW there can be a maximum of four chips on two buses with
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* two chip selects on each bus. We use four chip selects in SW
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* to differentiate between the four chips.
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* We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
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* SFB2AD accordingly.
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* We divide the total memory region size equally for each chip
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* and set SFA1AD, SFA2AD, SFB1AD, SFB2AD accordingly.
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*/
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qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,
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qspi_writel(q, q->memmap_phy_size / 4 + addr_offset,
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base + QUADSPI_SFA1AD);
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qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,
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qspi_writel(q, q->memmap_phy_size / 4 * 2 + addr_offset,
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base + QUADSPI_SFA2AD);
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qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,
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qspi_writel(q, q->memmap_phy_size / 4 * 3 + addr_offset,
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base + QUADSPI_SFB1AD);
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qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,
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qspi_writel(q, q->memmap_phy_size / 4 * 4 + addr_offset,
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base + QUADSPI_SFB2AD);
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q->selected = -1;
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@ -831,13 +876,8 @@ static int fsl_qspi_probe(struct platform_device *pdev)
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"QuadSPI-memory");
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q->ahb_addr = devm_ioremap_resource(dev, res);
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if (IS_ERR(q->ahb_addr)) {
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ret = PTR_ERR(q->ahb_addr);
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goto err_put_ctrl;
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}
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q->memmap_phy = res->start;
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q->memmap_phy_size = resource_size(res);
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/* find the clocks */
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q->clk_en = devm_clk_get(dev, "qspi_en");
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@ -911,6 +951,9 @@ static int fsl_qspi_remove(struct platform_device *pdev)
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mutex_destroy(&q->lock);
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if (q->ahb_addr)
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iounmap(q->ahb_addr);
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return 0;
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}
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