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drm/nouveau/fifo/gm200-: read pbdma count more directly 

The trick we used (and still use for older GPUs) doesn't work on Turing.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
hifive-unleashed-5.1
Ben Skeggs 2018-12-11 14:50:02 +10:00
parent f37a302e67
commit f7cc47e436
8 changed files with 36 additions and 8 deletions
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14
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
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@ -256,8 +256,18 @@ gk104_fifo_pbdma_init(struct gk104_fifo *fifo)
nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
}
int
gk104_fifo_pbdma_nr(struct gk104_fifo *fifo)
{
struct nvkm_device *device = fifo->base.engine.subdev.device;
/* Determine number of PBDMAs by checking valid enable bits. */
nvkm_wr32(device, 0x000204, 0xffffffff);
return hweight32(nvkm_rd32(device, 0x000204));
}
const struct gk104_fifo_pbdma_func
gk104_fifo_pbdma = {
.nr = gk104_fifo_pbdma_nr,
.init = gk104_fifo_pbdma_init,
};
@ -925,9 +935,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
enum nvkm_devidx engidx;
u32 *map;
/* Determine number of PBDMAs by checking valid enable bits. */
nvkm_wr32(device, 0x000204, 0xffffffff);
fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204));
fifo->pbdma_nr = fifo->func->pbdma->nr(fifo);
nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
/* Read PBDMA->runlist(s) mapping from HW. */

5
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
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@ -46,6 +46,7 @@ struct gk104_fifo {
struct gk104_fifo_func {
const struct gk104_fifo_pbdma_func {
int (*nr)(struct gk104_fifo *);
void (*init)(struct gk104_fifo *);
void (*init_timeout)(struct gk104_fifo *);
} *pbdma;
@ -89,6 +90,7 @@ void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *);
void gk104_fifo_runlist_update(struct gk104_fifo *, int runl);
extern const struct gk104_fifo_pbdma_func gk104_fifo_pbdma;
int gk104_fifo_pbdma_nr(struct gk104_fifo *);
void gk104_fifo_pbdma_init(struct gk104_fifo *);
extern const struct nvkm_enum gk104_fifo_fault_access[];
extern const struct nvkm_enum gk104_fifo_fault_engine[];
@ -111,5 +113,8 @@ void gk208_fifo_pbdma_init_timeout(struct gk104_fifo *);
extern const struct nvkm_enum gm107_fifo_fault_engine[];
extern const struct gk104_fifo_runlist_func gm107_fifo_runlist;
extern const struct gk104_fifo_pbdma_func gm200_fifo_pbdma;
int gm200_fifo_pbdma_nr(struct gk104_fifo *);
extern const struct nvkm_enum gp100_fifo_fault_engine[];
#endif

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
View File

@ -38,6 +38,7 @@ gk208_fifo_pbdma_init_timeout(struct gk104_fifo *fifo)
const struct gk104_fifo_pbdma_func
gk208_fifo_pbdma = {
.nr = gk104_fifo_pbdma_nr,
.init = gk104_fifo_pbdma_init,
.init_timeout = gk208_fifo_pbdma_init_timeout,
};

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c
View File

@ -26,9 +26,23 @@
#include <nvif/class.h>
int
gm200_fifo_pbdma_nr(struct gk104_fifo *fifo)
{
struct nvkm_device *device = fifo->base.engine.subdev.device;
return nvkm_rd32(device, 0x002004) & 0x000000ff;
}
const struct gk104_fifo_pbdma_func
gm200_fifo_pbdma = {
.nr = gm200_fifo_pbdma_nr,
.init = gk104_fifo_pbdma_init,
.init_timeout = gk208_fifo_pbdma_init_timeout,
};
static const struct gk104_fifo_func
gm200_fifo = {
.pbdma = &gk208_fifo_pbdma,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gm107_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
View File

@ -26,7 +26,7 @@
static const struct gk104_fifo_func
gm20b_fifo = {
.pbdma = &gk208_fifo_pbdma,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gm107_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
View File

@ -52,7 +52,7 @@ gp100_fifo_fault_engine[] = {
static const struct gk104_fifo_func
gp100_fifo = {
.pbdma = &gk208_fifo_pbdma,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gp100_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c
View File

@ -26,7 +26,7 @@
static const struct gk104_fifo_func
gp10b_fifo = {
.pbdma = &gk208_fifo_pbdma,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gk104_fifo_fault_access,
.fault.engine = gp100_fifo_fault_engine,
.fault.reason = gk104_fifo_fault_reason,

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.c
View File

@ -288,7 +288,7 @@ gv100_fifo_fault_access[] = {
static const struct gk104_fifo_func
gv100_fifo = {
.pbdma = &gk208_fifo_pbdma,
.pbdma = &gm200_fifo_pbdma,
.fault.access = gv100_fifo_fault_access,
.fault.engine = gv100_fifo_fault_engine,
.fault.reason = gv100_fifo_fault_reason,