ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlxh4LQACgkQWTcYmtP7 xmWu3w//bOc1aqMh325KmhP+WXUJEp0Z+7/r8TcqYYW2UMdjqGKvYNREaL+cDKu3 6DOaWvTKrRHOJr1L4uSdg1NBEhH6Nzmb7r9bRLkj2xT5vT66pZIiMa4OETfvdvP2 TQ86MPUY69M6IJ2JzeYA34stItYanExDhosbaHmPSJqwvDdh0V932eBg4OY/IpEn j4Hygf9HYSA5cSx7J2Ah1gUXzI66FcPlRBWrl+jeTS7qqU9GxYo8/8Hrgn6hyCTQ dpQHvgsCdeHvsf8fRpulxH/aUo5u2nuX1/R8UrOWUmCPd2r3RBu0U27Ja7FJiAeb s6OwLveAVeMS7Urrh3ylaFstbjg3CMtGvh1hnbWozF08yNzd6ihD5vsUED7vpxNr hT8m8oC8hujP1CiIxFqbkPZsz/hWoagPOG2AtRNMehs+gVxOfD+CTkw3Y+x3+NrA DwU9YzrKqFn4StSHJ6ccBE857gSH5QgOq0rLYiH1AlktHvXKh/hL/H82pFDJHZcW OFZ2nAI9VCPDlx8tCbuH16BIqD03piT5ew0wWozG5uc/JP26stmMXHQlQVDxRju4 NsJiqGzAtgIK+jf2COVZJeYtOO9IYjPwrC0wJe2vWW7MTUBv0LSQDuBV2pTT/N87 pSqeusg80DuPC3WZLGU3whitwO6yg3NiWeGB6cweu3gWeQsMSig= =PNC5 -----END PGP SIGNATURE----- Merge tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.1 - more features for Endless EC100 board - chip temperature sensor support - fix ethernet pins - add Mali-450 GPU * tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: ec100: add the GPIO line names ARM: dts: meson8b: ec100: improve the description of the regulators ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature ARM: dts: meson8b: add the temperature calibration data for the SAR ADC ARM: dts: meson8: add the temperature calibration data for the SAR ADC ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible ARM: dts: meson: switch the clock controller to the HHI register area ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins ARM: dts: meson8b: add the Mali-450 MP2 GPU ARM: dts: meson8: add the Mali-450 MP6 GPU dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible ARM: dts: meson8b: add the APB bus ARM: dts: meson8: add the APB bus ARM: dts: meson6: add the APB2 bus Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
commit
f815bb4e97
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@ -13,6 +13,8 @@ Required properties:
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+ allwinner,sun8i-h3-mali
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+ allwinner,sun50i-a64-mali
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+ allwinner,sun50i-h5-mali
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+ amlogic,meson8-mali
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+ amlogic,meson8b-mali
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+ amlogic,meson-gxbb-mali
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+ amlogic,meson-gxl-mali
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+ rockchip,rk3036-mali
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@ -82,6 +84,10 @@ to specify one more vendor-specific compatible, among:
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Required properties:
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* resets: phandle to the reset line for the GPU
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- amlogic,meson8-mali and amlogic,meson8b-mali
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Required properties:
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* resets: phandle to the reset line for the GPU
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- Rockchip variants:
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Required properties:
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* resets: phandle to the reset line for the GPU
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@ -73,6 +73,13 @@
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#size-cells = <1>;
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ranges = <0x0 0xc1100000 0x200000>;
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hhi: system-controller@4000 {
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compatible = "amlogic,meson-hhi-sysctrl",
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"simple-mfd",
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"syscon";
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reg = <0x4000 0x400>;
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};
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assist: assist@7c00 {
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compatible = "amlogic,meson-mx-assist", "syscon";
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reg = <0x7c00 0x200>;
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@ -70,6 +70,14 @@
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};
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};
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apb2: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x40000>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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@ -166,6 +166,32 @@
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};
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-182150000 {
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opp-hz = /bits/ 64 <182150000>;
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opp-microvolt = <1150000>;
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};
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opp-318750000 {
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opp-hz = /bits/ 64 <318750000>;
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opp-microvolt = <1150000>;
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};
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opp-425000000 {
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opp-hz = /bits/ 64 <425000000>;
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opp-microvolt = <1150000>;
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};
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opp-510000000 {
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opp-hz = /bits/ 64 <510000000>;
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opp-microvolt = <1150000>;
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};
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opp-637500000 {
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opp-hz = /bits/ 64 <637500000>;
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opp-microvolt = <1150000>;
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turbo-mode;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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@ -201,6 +227,46 @@
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no-map;
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};
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};
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apb: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x200000>;
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mali: gpu@c0000 {
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compatible = "amlogic,meson8-mali", "arm,mali-450";
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reg = <0xc0000 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1",
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"pp2", "ppmmu2", "pp4", "ppmmu4",
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"pp5", "ppmmu5", "pp6", "ppmmu6";
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resets = <&reset RESET_MALI>;
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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operating-points-v2 = <&gpu_opp_table>;
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switch-delay = <0xffff>;
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};
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};
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}; /* end of / */
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&aobus {
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@ -261,13 +327,6 @@
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};
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&cbus {
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clkc: clock-controller@4000 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "amlogic,meson8-clkc";
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reg = <0x8000 0x4>, <0x4000 0x400>;
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};
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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@ -390,6 +449,11 @@
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compatible = "amlogic,meson8-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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clock-names = "core";
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temperature_calib: calib@1f4 {
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/* only the upper two bytes are relevant */
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reg = <0x1f4 0x4>;
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};
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};
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ðmac {
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@ -402,6 +466,14 @@
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status = "okay";
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};
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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&hwrng {
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compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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@ -469,6 +541,9 @@
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clocks = <&clkc CLKID_XTAL>,
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<&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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amlogic,hhi-sysctrl = <&hhi>;
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nvmem-cells = <&temperature_calib>;
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nvmem-cell-names = "temperature_calib";
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};
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&sdio {
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@ -65,6 +65,11 @@
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timeout-ms = <20000>;
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&saradc 8>;
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};
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leds {
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compatible = "gpio-leds";
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@ -84,6 +89,9 @@
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};
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usb_vbus: regulator-usb-vbus {
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/*
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* Silergy SY6288CCAC-GP 2A Power Distribution Switch.
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*/
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compatible = "regulator-fixed";
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regulator-name = "USB_VBUS";
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@ -91,11 +99,20 @@
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc_5v>;
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/*
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* signal name from the schematics: USB_PWR_EN
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*/
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gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vcc_5v: regulator-vcc5v {
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/*
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* supplied by the main power input which called PWR_5V_STB
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* in the schematics
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*/
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compatible = "regulator-fixed";
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regulator-name = "VCC5V";
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@ -103,6 +120,9 @@
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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/*
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* signal name from the schematics: 3V3_5V_EN
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*/
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gpio = <&gpio GPIODV_29 GPIO_ACTIVE_LOW>;
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regulator-boot-on;
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@ -110,12 +130,18 @@
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};
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vcck: regulator-vcck {
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/*
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* Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
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* Synchronous Step Down Regulator.
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*/
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compatible = "pwm-regulator";
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regulator-name = "VCCK";
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regulator-min-microvolt = <860000>;
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regulator-max-microvolt = <1140000>;
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vin-supply = <&vcc_5v>;
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pwms = <&pwm_cd 0 1148 0>;
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pwm-dutycycle-range = <100 0>;
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@ -124,19 +150,66 @@
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};
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vcc_1v8: regulator-vcc1v8 {
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/*
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* ABLIC S-1339D18-M5001-GP
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*/
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compatible = "regulator-fixed";
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regulator-name = "VCC1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc_3v3>;
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};
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vcc_3v3: regulator-vcc3v3 {
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/*
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* Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
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* Synchronous Step Down Regulator. Also called
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* VDDIO_AO3.3V in the schematics.
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*/
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compatible = "regulator-fixed";
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regulator-name = "VCC3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc_5v>;
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};
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vcc_ddr3: regulator-vcc-ddr3 {
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/*
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* Silergy SY8089AAC-GP 2A continuous, 3A peak, 1MHz
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* Synchronous Step Down Regulator. Also called
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* DDR3_1.5V in the schematics.
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*/
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compatible = "regulator-fixed";
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regulator-name = "VCC_DDR3_1V5";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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vin-supply = <&vcc_5v>;
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regulator-boot-on;
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regulator-always-on;
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};
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vcc_rtc: regulator-vcc-rtc {
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/*
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* Global Mixed-mode Technology Inc. G918T12U-GP
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*/
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compatible = "regulator-fixed";
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regulator-name = "VCC_RTC";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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/*
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* When the board is powered then the input is VCC3V3,
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* otherwise power is taken from the coin cell battery.
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*/
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vin-supply = <&vcc_3v3>;
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};
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};
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@ -165,6 +238,10 @@
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eth_phy0: ethernet-phy@0 {
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/* IC Plus IP101A/G (0x02430c54) */
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reg = <0>;
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icplus,select-interrupt;
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interrupt-parent = <&gpio_intc>;
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/* GPIOH_3 */
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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@ -213,6 +290,56 @@
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};
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};
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&gpio_ao {
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gpio-line-names = "Linux_TX", "Linux_RX",
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"SLP_S5_N", "USB2_OC_FLAG#",
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"HUB_RST", "USB_PWR_EN",
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"I2S_IN", "SLP_S1_N",
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"TCK", "TMS", "TDI", "TDO",
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"HDMI_CEC", "5640_IRQ",
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"MUTE", "S805_TEST#";
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};
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&gpio {
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gpio-line-names = /* Bank GPIOX */
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"WIFI_SD_D0", "WIFI_SD_D1", "WIFI_SD_D2",
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"WIFI_SD_D3", "BTPCM_DOUT", "BTPCM_DIN",
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"BTPCM_SYNC", "BTPCM_CLK", "WIFI_SD_CLK",
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"WIFI_SD_CMD", "WIFI_32K", "WIFI_PWREN",
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"UART_B_TX", "UART_B_RX", "UART_B_CTS_N",
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"UART_B_RTS_N", "BT_EN", "WIFI_WAKE_HOST",
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/* Bank GPIOY */
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"", "", "", "", "", "", "", "", "", "",
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"", "",
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/* Bank GPIODV */
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"VCCK_PWM_C", "I2C_SDA_A", "I2C_SCL_A",
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"I2C_SDA_B", "I2C_SCL_B", "VDDEE_PWM_D",
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"VDDEE_PWM 3V3_5V_EN",
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/* Bank GPIOH */
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"HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL",
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"RMII_IRQ", "RMII_RST#", "RMII_TXD1",
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"RMII_TXD0", "AV_select_1", "AV_select_2",
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"MCU_Control_S",
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/* Bank CARD */
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"SD_D1_B", "SD_D0_B", "SD_CLK_8726MX",
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"SD_CMD_8726MX", "SD_D3_B", "SD_D2_B",
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"CARD_EN_DET (CARD_DET)",
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/* Bank BOOT */
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"NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
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"NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
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"NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
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"NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
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"NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
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"NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
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"NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
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"nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS",
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/* Bank DIF */
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"RMII_RXD1", "RMII_RXD0", "RMII_CRS_DV",
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"RMII_50M_IN", "GPIODIF_4", "GPIODIF_5",
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"RMII_TXEN", "CPUETH_25MOUT", "RMII_MDC",
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"RMII_MDIO";
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};
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&pwm_cd {
|
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>;
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@ -119,6 +119,11 @@
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1800000 1>;
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};
|
||||
|
||||
iio-hwmon {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&saradc 8>;
|
||||
};
|
||||
|
||||
vcc_1v8: regulator-vcc-1v8 {
|
||||
/*
|
||||
* RICHTEK RT9179 configured for a fixed output voltage of
|
||||
|
|
|
|||
|
|
@ -158,6 +158,32 @@
|
|||
};
|
||||
};
|
||||
|
||||
gpu_opp_table: gpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-255000000 {
|
||||
opp-hz = /bits/ 64 <255000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp-364300000 {
|
||||
opp-hz = /bits/ 64 <364300000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp-425000000 {
|
||||
opp-hz = /bits/ 64 <425000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp-510000000 {
|
||||
opp-hz = /bits/ 64 <510000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp-637500000 {
|
||||
opp-hz = /bits/ 64 <637500000>;
|
||||
opp-microvolt = <1150000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a5-pmu";
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -178,6 +204,34 @@
|
|||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
apb: bus@d0000000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0xd0000000 0x200000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xd0000000 0x200000>;
|
||||
|
||||
mali: gpu@c0000 {
|
||||
compatible = "amlogic,meson8b-mali", "arm,mali-450";
|
||||
reg = <0xc0000 0x40000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gp", "gpmmu", "pp", "pmu",
|
||||
"pp0", "ppmmu0", "pp1", "ppmmu1";
|
||||
resets = <&reset RESET_MALI>;
|
||||
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
|
||||
clock-names = "bus", "core";
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
switch-delay = <0xffff>;
|
||||
};
|
||||
};
|
||||
}; /* end of / */
|
||||
|
||||
&aobus {
|
||||
|
|
@ -222,13 +276,6 @@
|
|||
};
|
||||
|
||||
&cbus {
|
||||
clkc: clock-controller@4000 {
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
compatible = "amlogic,meson8b-clkc";
|
||||
reg = <0x8000 0x4>, <0x4000 0x400>;
|
||||
};
|
||||
|
||||
reset: reset-controller@4404 {
|
||||
compatible = "amlogic,meson8b-reset";
|
||||
reg = <0x4404 0x9c>;
|
||||
|
|
@ -270,9 +317,7 @@
|
|||
groups = "eth_tx_clk",
|
||||
"eth_tx_en",
|
||||
"eth_txd1_0",
|
||||
"eth_txd1_1",
|
||||
"eth_txd0_0",
|
||||
"eth_txd0_1",
|
||||
"eth_rx_clk",
|
||||
"eth_rx_dv",
|
||||
"eth_rxd1",
|
||||
|
|
@ -281,7 +326,9 @@
|
|||
"eth_mdc",
|
||||
"eth_ref_clk",
|
||||
"eth_txd2",
|
||||
"eth_txd3";
|
||||
"eth_txd3",
|
||||
"eth_rxd3",
|
||||
"eth_rxd2";
|
||||
function = "ethernet";
|
||||
bias-disable;
|
||||
};
|
||||
|
|
@ -360,6 +407,11 @@
|
|||
compatible = "amlogic,meson8b-efuse";
|
||||
clocks = <&clkc CLKID_EFUSE>;
|
||||
clock-names = "core";
|
||||
|
||||
temperature_calib: calib@1f4 {
|
||||
/* only the upper two bytes are relevant */
|
||||
reg = <0x1f4 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
ðmac {
|
||||
|
|
@ -383,6 +435,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hhi {
|
||||
clkc: clock-controller {
|
||||
compatible = "amlogic,meson8-clkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&hwrng {
|
||||
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
|
||||
clocks = <&clkc CLKID_RNG0>;
|
||||
|
|
@ -450,6 +510,9 @@
|
|||
clocks = <&clkc CLKID_XTAL>,
|
||||
<&clkc CLKID_SAR_ADC>;
|
||||
clock-names = "clkin", "core";
|
||||
amlogic,hhi-sysctrl = <&hhi>;
|
||||
nvmem-cells = <&temperature_calib>;
|
||||
nvmem-cell-names = "temperature_calib";
|
||||
};
|
||||
|
||||
&sdio {
|
||||
|
|
|
|||
|
|
@ -45,6 +45,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
iio-hwmon {
|
||||
compatible = "iio-hwmon";
|
||||
io-channels = <&saradc 8>;
|
||||
};
|
||||
|
||||
vcc_3v3: regulator-vcc3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VCC3V3";
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt";
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue