MIPS: mscc: Add jaguar2 support
Add a device trees and FIT image support for the Microsemi Jaguar2 SoC which belongs to same family of the Ocelot SoC. It is based on the work of Lars Povlsen <lars.povlsen@microchip.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>zero-sugar-mainline-defconfig
Gregory CLEMENT
Thomas Bogendoerfer
parent
378e413fe9
commit
f84778f7d8
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@ -1,5 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-only
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dtb-$(CONFIG_SOC_VCOREIII) += \
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jaguar2_pcb110.dtb \
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jaguar2_pcb111.dtb \
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jaguar2_pcb118.dtb \
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luton_pcb091.dtb \
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ocelot_pcb120.dtb \
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ocelot_pcb123.dtb
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@ -0,0 +1,167 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microsemi Corporation
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,jr2";
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aliases {
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serial0 = &uart0;
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serial1 = &uart2;
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gpio0 = &gpio;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&cpu_clk>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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ahb: ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@70000000 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x70000000 0x2c>;
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};
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intc: interrupt-controller@70000070 {
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compatible = "mscc,jaguar2-icpu-intr";
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reg = <0x70000070 0x94>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@70100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x70100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@70100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x70100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio: pinctrl@71010038 {
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compatible = "mscc,jaguar2-pinctrl";
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reg = <0x71010038 0x90>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 64>;
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uart_pins: uart-pins {
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pins = "GPIO_10", "GPIO_11";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_24", "GPIO_25";
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function = "uart2";
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};
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cs1_pins: cs1-pins {
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pins = "GPIO_16";
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function = "si";
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};
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cs2_pins: cs2-pins {
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pins = "GPIO_17";
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function = "si";
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};
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cs3_pins: cs3-pins {
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pins = "GPIO_18";
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function = "si";
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};
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i2c_pins: i2c-pins {
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pins = "GPIO_14", "GPIO_15";
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function = "twi";
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};
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i2c2_pins: i2c2-pins {
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pins = "GPIO_28", "GPIO_29";
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function = "twi2";
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};
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};
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i2c0: i2c@70100400 {
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compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c_pins>;
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pinctrl-names = "default";
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reg = <0x70100400 0x100>, <0x700001b8 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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i2c2: i2c@70100c00 {
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compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
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status = "disabled";
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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reg = <0x70100c00 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <8>;
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clock-frequency = <100000>;
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clocks = <&ahb_clk>;
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};
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};
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};
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@ -0,0 +1,25 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microsemi Corporation
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*/
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#include "jaguar2.dtsi"
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/ {
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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i2c-sda-hold-time-ns = <300>;
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};
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@ -0,0 +1,267 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Microsemi Corporation
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*/
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/dts-v1/;
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#include "jaguar2_common.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
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compatible = "mscc,jr2-pcb110", "mscc,jr2";
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aliases {
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i2c0 = &i2c0;
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i2c108 = &i2c108;
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i2c109 = &i2c109;
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i2c110 = &i2c110;
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i2c111 = &i2c111;
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i2c112 = &i2c112;
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i2c113 = &i2c113;
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i2c114 = &i2c114;
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i2c115 = &i2c115;
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i2c116 = &i2c116;
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i2c117 = &i2c117;
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i2c118 = &i2c118;
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i2c119 = &i2c119;
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i2c120 = &i2c120;
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i2c121 = &i2c121;
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i2c122 = &i2c122;
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i2c123 = &i2c123;
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i2c124 = &i2c124;
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i2c125 = &i2c125;
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i2c126 = &i2c126;
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i2c127 = &i2c127;
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i2c128 = &i2c128;
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i2c129 = &i2c129;
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i2c130 = &i2c130;
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i2c131 = &i2c131;
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i2c149 = &i2c149;
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i2c150 = &i2c150;
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i2c151 = &i2c151;
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i2c152 = &i2c152;
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};
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i2c0_imux: i2c0-imux {
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compatible = "i2c-mux-pinctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
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pinctrl-names =
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"i2c149", "i2c150", "i2c151", "i2c152", "idle";
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pinctrl-0 = <&i2cmux_0>;
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pinctrl-1 = <&i2cmux_1>;
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pinctrl-2 = <&i2cmux_2>;
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pinctrl-3 = <&i2cmux_3>;
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pinctrl-4 = <&i2cmux_pins_i>;
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i2c149: i2c@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c150: i2c@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c151: i2c@2 {
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reg = <0x2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c152: i2c@3 {
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reg = <0x3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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i2c0_emux: i2c0-emux {
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compatible = "i2c-mux-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c0>;
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mux-gpios = <&gpio 51 GPIO_ACTIVE_HIGH
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&gpio 52 GPIO_ACTIVE_HIGH
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&gpio 53 GPIO_ACTIVE_HIGH
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&gpio 58 GPIO_ACTIVE_HIGH
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&gpio 59 GPIO_ACTIVE_HIGH>;
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idle-state = <0x0>;
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i2c108: i2c@10 {
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reg = <0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c109: i2c@11 {
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reg = <0x11>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c110: i2c@12 {
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reg = <0x12>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c111: i2c@13 {
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reg = <0x13>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c112: i2c@14 {
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reg = <0x14>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c113: i2c@15 {
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reg = <0x15>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c114: i2c@16 {
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reg = <0x16>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c115: i2c@17 {
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reg = <0x17>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c116: i2c@8 {
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reg = <0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c117: i2c@9 {
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reg = <0x9>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c118: i2c@a {
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reg = <0xa>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c119: i2c@b {
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reg = <0xb>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c120: i2c@c {
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reg = <0xc>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c121: i2c@d {
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reg = <0xd>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c122: i2c@e {
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reg = <0xe>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c123: i2c@f {
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reg = <0xf>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&gpio {
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synce_pins: synce-pins {
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// GPIO 16 == SI_nCS1
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pins = "GPIO_16";
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function = "si";
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};
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synce_builtin_pins: synce-builtin-pins {
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// GPIO 49 == SI_nCS13
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pins = "GPIO_49";
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function = "si";
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};
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i2cmux_pins_i: i2cmux-pins-i {
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pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
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function = "twi_scl_m";
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output-low;
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};
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i2cmux_0: i2cmux-0 {
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pins = "GPIO_17";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_1: i2cmux-1 {
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pins = "GPIO_18";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_2: i2cmux-2 {
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pins = "GPIO_20";
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function = "twi_scl_m";
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output-high;
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};
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i2cmux_3: i2cmux-3 {
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pins = "GPIO_21";
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function = "twi_scl_m";
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output-high;
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};
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};
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&i2c0 {
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pca9545@70 {
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compatible = "nxp,pca9545";
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reg = <0x70>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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i2c124: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c125: i2c@1 {
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/* FMC B */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c126: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c127: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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pca9545@71 {
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compatible = "nxp,pca9545";
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-mux-idle-disconnect;
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i2c128: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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i2c129: i2c@1 {
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/* FMC B */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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};
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i2c130: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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};
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i2c131: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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};
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};
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};
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@ -0,0 +1,107 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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/dts-v1/;
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#include "jaguar2_common.dtsi"
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/ {
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model = "Jaguar2 Cu48 PCB111 Reference Board";
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compatible = "mscc,jr2-pcb111", "mscc,jr2";
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aliases {
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i2c0 = &i2c0;
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i2c149 = &i2c149;
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i2c150 = &i2c150;
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i2c151 = &i2c151;
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i2c152 = &i2c152;
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i2c203 = &i2c203;
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};
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|
||||
i2c0_imux: i2c0-imux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-parent = <&i2c0>;
|
||||
pinctrl-names =
|
||||
"i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
|
||||
pinctrl-0 = <&i2cmux_0>;
|
||||
pinctrl-1 = <&i2cmux_1>;
|
||||
pinctrl-2 = <&i2cmux_2>;
|
||||
pinctrl-3 = <&i2cmux_3>;
|
||||
pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
|
||||
pinctrl-5 = <&i2cmux_pins_i>;
|
||||
i2c149: i2c@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c150: i2c@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c151: i2c@2 {
|
||||
reg = <0x2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c152: i2c@3 {
|
||||
reg = <0x3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c203: i2c@4 {
|
||||
reg = <0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
synce_builtin_pins: synce-builtin-pins {
|
||||
// GPIO 49 == SI_nCS13
|
||||
pins = "GPIO_49";
|
||||
function = "si";
|
||||
};
|
||||
cpld_pins: cpld-pins {
|
||||
// GPIO 50 == SI_nCS14
|
||||
pins = "GPIO_50";
|
||||
function = "si";
|
||||
};
|
||||
cpld_fifo_pins: synce-builtin-pins {
|
||||
// GPIO 51 == SI_nCS15
|
||||
pins = "GPIO_51";
|
||||
function = "si";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2cmux_pins_i: i2cmux-pins-i {
|
||||
pins = "GPIO_17", "GPIO_18";
|
||||
function = "twi_scl_m";
|
||||
output-low;
|
||||
};
|
||||
i2cmux_0: i2cmux-0 {
|
||||
pins = "GPIO_17";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_1: i2cmux-1 {
|
||||
pins = "GPIO_18";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_2: i2cmux-2 {
|
||||
pins = "GPIO_20";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_3: i2cmux-3 {
|
||||
pins = "GPIO_21";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2018 Microsemi Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jaguar2_common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Jaguar2/Aquantia PCB118 Reference Board";
|
||||
compatible = "mscc,jr2-pcb118", "mscc,jr2";
|
||||
|
||||
aliases {
|
||||
i2c150 = &i2c150;
|
||||
i2c151 = &i2c151;
|
||||
};
|
||||
|
||||
i2c0_imux: i2c0-imux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
i2c-parent = <&i2c0>;
|
||||
pinctrl-names =
|
||||
"i2c150", "i2c151", "idle";
|
||||
pinctrl-0 = <&i2cmux_0>;
|
||||
pinctrl-1 = <&i2cmux_1>;
|
||||
pinctrl-2 = <&i2cmux_pins_i>;
|
||||
i2c150: i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
i2c151: i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2cmux_pins_i: i2cmux-pins-i {
|
||||
pins = "GPIO_17", "GPIO_16";
|
||||
function = "twi_scl_m";
|
||||
output-low;
|
||||
};
|
||||
i2cmux_0: i2cmux-0 {
|
||||
pins = "GPIO_17";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
i2cmux_1: i2cmux-1 {
|
||||
pins = "GPIO_16";
|
||||
function = "twi_scl_m";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
|
@ -86,6 +86,14 @@ config FIT_IMAGE_FDT_LUTON
|
|||
from Microsemi in the FIT kernel image.
|
||||
This requires u-boot on the platform.
|
||||
|
||||
config FIT_IMAGE_FDT_JAGUAR2
|
||||
bool "Include FDT for Microsemi Jaguar2 development platforms"
|
||||
select SOC_VCOREIII
|
||||
help
|
||||
Enable this to include the FDT for the Jaguar2 development platforms
|
||||
from Microsemi in the FIT kernel image.
|
||||
This requires u-boot on the platform.
|
||||
|
||||
config BOARD_INGENIC
|
||||
bool "Support boards based on Ingenic SoCs"
|
||||
select MACH_INGENIC_GENERIC
|
||||
|
|
|
|||
|
|
@ -21,4 +21,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
|
|||
its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
|
||||
its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
|
||||
its-$(CONFIG_FIT_IMAGE_FDT_LUTON) += board-luton.its.S
|
||||
its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S
|
||||
its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/ {
|
||||
images {
|
||||
fdt@jaguar2_pcb110 {
|
||||
description = "MSCC Jaguar2 PCB110 Device Tree";
|
||||
data = /incbin/("boot/dts/mscc/jaguar2_pcb110.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "mips";
|
||||
compression = "none";
|
||||
hash@0 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
fdt@jaguar2_pcb111 {
|
||||
description = "MSCC Jaguar2 PCB111 Device Tree";
|
||||
data = /incbin/("boot/dts/mscc/jaguar2_pcb111.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "mips";
|
||||
compression = "none";
|
||||
hash@0 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
pcb110 {
|
||||
description = "Jaguar2 Linux kernel";
|
||||
kernel = "kernel@0";
|
||||
fdt = "fdt@jaguar2_pcb110";
|
||||
ramdisk = "ramdisk";
|
||||
};
|
||||
pcb111 {
|
||||
description = "Jaguar2 Linux kernel";
|
||||
kernel = "kernel@0";
|
||||
fdt = "fdt@jaguar2_pcb111";
|
||||
ramdisk = "ramdisk";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue