drm/radeon/kms/igp: fix possible divide by 0 in bandwidth code (v2)
Some IGP systems specify the system memory clock in the Firmware table rather than the IGP info table. Check both and make sure we have a value system memory clock value. v2: make sure rs690_pm_info is called on rs780/rs880 as well. fixes a regression since 07d4190327b02ab3aaad25a2d168f79d92e8f8c2. Reported-by: Markus Trippelsdorf <markus@trippelsdorf.de> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Tested-by: Markus Trippelsdorf <markus@trippelsdorf.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -1219,8 +1219,10 @@ int r600_mc_init(struct radeon_device *rdev)
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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r600_vram_gtt_location(rdev, &rdev->mc);
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if (rdev->flags & RADEON_IS_IGP)
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if (rdev->flags & RADEON_IS_IGP) {
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rs690_pm_info(rdev);
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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}
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radeon_update_bandwidth_info(rdev);
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return 0;
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}
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@ -177,6 +177,7 @@ void radeon_pm_resume(struct radeon_device *rdev);
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void radeon_combios_get_power_modes(struct radeon_device *rdev);
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void radeon_atombios_get_power_modes(struct radeon_device *rdev);
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void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
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void rs690_pm_info(struct radeon_device *rdev);
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/*
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* Fences.
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@ -79,7 +79,13 @@ void rs690_pm_info(struct radeon_device *rdev)
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tmp.full = dfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
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rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
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if (info->info.usK8MemoryClock)
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rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
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else if (rdev->clock.default_mclk) {
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rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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} else
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rdev->pm.igp_system_mclk.full = dfixed_const(400);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
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rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
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break;
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@ -87,34 +93,31 @@ void rs690_pm_info(struct radeon_device *rdev)
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tmp.full = dfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
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rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
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if (info->info_v2.ulBootUpUMAClock)
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rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
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else if (rdev->clock.default_mclk)
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rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
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else
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rdev->pm.igp_system_mclk.full = dfixed_const(66700);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
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rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
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rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
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break;
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default:
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tmp.full = dfixed_const(100);
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/* We assume the slower possible clock ie worst case */
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/* DDR 333Mhz */
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rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
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/* FIXME: system clock ? */
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rdev->pm.igp_system_mclk.full = dfixed_const(100);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
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rdev->pm.igp_system_mclk.full = dfixed_const(200);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
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rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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break;
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}
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} else {
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tmp.full = dfixed_const(100);
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/* We assume the slower possible clock ie worst case */
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/* DDR 333Mhz */
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rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
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/* FIXME: system clock ? */
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rdev->pm.igp_system_mclk.full = dfixed_const(100);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
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rdev->pm.igp_system_mclk.full = dfixed_const(200);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
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rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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}
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