drm/radeon: improve PLL params if we don't match exactly v2
Otherwise we might be quite off on older chipsets. v2: keep ref_div minimum Signed-off-by: Christian König <christian.koenig@amd.com>
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@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
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unsigned post_div_min, post_div_max, post_div;
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unsigned ref_div_min, ref_div_max, ref_div;
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unsigned post_div_best, diff_best;
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unsigned nom, den, tmp;
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unsigned nom, den;
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/* determine allowed feedback divider range */
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fb_div_min = pll->min_feedback_div;
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@ -941,22 +941,23 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
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ref_div_max = min(210 / post_div, ref_div_max);
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/* get matching reference and feedback divider */
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ref_div = max(den / post_div, 1u);
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fb_div = nom;
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ref_div = max(DIV_ROUND_CLOSEST(den, post_div), 1u);
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fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
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/* we're almost done, but reference and feedback
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divider might be to large now */
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tmp = ref_div;
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nom = fb_div;
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den = ref_div;
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if (fb_div > fb_div_max) {
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ref_div = ref_div * fb_div_max / fb_div;
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ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
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fb_div = fb_div_max;
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}
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if (ref_div > ref_div_max) {
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ref_div = ref_div_max;
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fb_div = nom * ref_div_max / tmp;
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fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
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}
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/* reduce the numbers to a simpler ratio once more */
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