[media] marvell-cam: Move Cafe-specific register definitions to cafe-driver.c
Nobody else ever needs to see these, so let's hide them. Signed-off-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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Jonathan Corbet
Mauro Carvalho Chehab
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9eefa7dc01
commit
f8ff6a96cd
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@ -56,6 +56,69 @@ struct cafe_camera {
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wait_queue_head_t smbus_wait; /* Waiting on i2c events */
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};
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/*
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* Most of the camera controller registers are defined in mcam-core.h,
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* but the Cafe platform has some additional registers of its own;
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* they are described here.
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*/
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/*
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* "General purpose register" has a couple of GPIOs used for sensor
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* power and reset on OLPC XO 1.0 systems.
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*/
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#define REG_GPR 0xb4
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#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
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#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
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#define GPR_C1 0x00000002 /* Control 1 value */
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/*
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* Control 0 is wired to reset on OLPC machines. For ov7x sensors,
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* it is active low.
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*/
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#define GPR_C0 0x00000001 /* Control 0 value */
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/*
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* These registers control the SMBUS module for communicating
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* with the sensor.
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*/
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#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
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#define TWSIC0_EN 0x00000001 /* TWSI enable */
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#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
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#define TWSIC0_SID 0x000003fc /* Slave ID */
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#define TWSIC0_SID_SHIFT 2
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#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
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#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
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#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
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#define REG_TWSIC1 0xbc /* TWSI control 1 */
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#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
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#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
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#define TWSIC1_ADDR_SHIFT 16
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#define TWSIC1_READ 0x01000000 /* Set for read op */
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#define TWSIC1_WSTAT 0x02000000 /* Write status */
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#define TWSIC1_RVALID 0x04000000 /* Read data valid */
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#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
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/*
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* Here's the weird global control registers
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*/
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#define REG_GL_CSR 0x3004 /* Control/status register */
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#define GCSR_SRS 0x00000001 /* SW Reset set */
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#define GCSR_SRC 0x00000002 /* SW Reset clear */
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#define GCSR_MRS 0x00000004 /* Master reset set */
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#define GCSR_MRC 0x00000008 /* HW Reset clear */
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#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
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#define REG_GL_IMASK 0x300c /* Interrupt mask register */
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#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
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#define REG_GL_FCR 0x3038 /* GPIO functional control register */
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#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
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#define REG_GL_GPIOR 0x315c /* GPIO register */
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#define GGPIO_OUT 0x80000 /* GPIO output */
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#define GGPIO_VAL 0x00008 /* Output pin value */
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#define REG_LEN (REG_GL_IMASK + 4)
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/*
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* Debugging and related.
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*/
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@ -249,63 +249,9 @@ int mccic_resume(struct mcam_camera *cam);
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#define REG_CLKCTRL 0x88 /* Clock control */
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#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
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#define REG_GPR 0xb4 /* General purpose register. This
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controls inputs to the power and reset
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pins on the OV7670 used with OLPC;
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other deployments could differ. */
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#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
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#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
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#define GPR_C1 0x00000002 /* Control 1 value */
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/*
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* Control 0 is wired to reset on OLPC machines. For ov7x sensors,
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* it is active low, for 0v6x, instead, it's active high. What
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* fun.
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*/
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#define GPR_C0 0x00000001 /* Control 0 value */
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#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
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#define TWSIC0_EN 0x00000001 /* TWSI enable */
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#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
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#define TWSIC0_SID 0x000003fc /* Slave ID */
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#define TWSIC0_SID_SHIFT 2
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#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
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#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
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#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
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#define REG_TWSIC1 0xbc /* TWSI control 1 */
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#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
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#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
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#define TWSIC1_ADDR_SHIFT 16
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#define TWSIC1_READ 0x01000000 /* Set for read op */
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#define TWSIC1_WSTAT 0x02000000 /* Write status */
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#define TWSIC1_RVALID 0x04000000 /* Read data valid */
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#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
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/* This appears to be a Cafe-only register */
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#define REG_UBAR 0xc4 /* Upper base address register */
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/*
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* Here's the weird global control registers which are said to live
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* way up here.
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*/
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#define REG_GL_CSR 0x3004 /* Control/status register */
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#define GCSR_SRS 0x00000001 /* SW Reset set */
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#define GCSR_SRC 0x00000002 /* SW Reset clear */
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#define GCSR_MRS 0x00000004 /* Master reset set */
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#define GCSR_MRC 0x00000008 /* HW Reset clear */
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#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
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#define REG_GL_IMASK 0x300c /* Interrupt mask register */
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#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
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#define REG_GL_FCR 0x3038 /* GPIO functional control register */
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#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
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#define REG_GL_GPIOR 0x315c /* GPIO register */
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#define GGPIO_OUT 0x80000 /* GPIO output */
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#define GGPIO_VAL 0x00008 /* Output pin value */
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#define REG_LEN (REG_GL_IMASK + 4)
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/*
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* Useful stuff that probably belongs somewhere global.
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*/
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