gma500: Add the glue to the various BIOS and firmware interfaces
Some of this should one day become a library shared by i915 and gma500 I suspct. Best however to deal with that later once it is all nice and stably merged. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>hifive-unleashed-5.1
Alan Cox
Dave Airlie
parent
bbbb262d37
commit
f910b41105
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/*
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* Copyright (c) 2006 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include <drm/drmP.h>
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#include <drm/drm.h>
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#include "psb_drm.h"
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "intel_bios.h"
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static void *find_section(struct bdb_header *bdb, int section_id)
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{
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u8 *base = (u8 *)bdb;
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int index = 0;
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u16 total, current_size;
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u8 current_id;
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/* skip to first section */
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index += bdb->header_size;
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total = bdb->bdb_size;
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/* walk the sections looking for section_id */
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while (index < total) {
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current_id = *(base + index);
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index++;
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current_size = *((u16 *)(base + index));
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index += 2;
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if (current_id == section_id)
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return base + index;
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index += current_size;
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}
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return NULL;
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}
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static void fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
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struct lvds_dvo_timing *dvo_timing)
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{
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panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
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dvo_timing->hactive_lo;
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panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
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((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
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panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
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dvo_timing->hsync_pulse_width;
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panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
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((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
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panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
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dvo_timing->vactive_lo;
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panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
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dvo_timing->vsync_off;
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panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
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dvo_timing->vsync_pulse_width;
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panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
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((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
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panel_fixed_mode->clock = dvo_timing->clock * 10;
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panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
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/* Some VBTs have bogus h/vtotal values */
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if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
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panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
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if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
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panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
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drm_mode_set_name(panel_fixed_mode);
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}
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static void parse_backlight_data(struct drm_psb_private *dev_priv,
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struct bdb_header *bdb)
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{
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struct bdb_lvds_backlight *vbt_lvds_bl = NULL;
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struct bdb_lvds_backlight *lvds_bl;
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u8 p_type = 0;
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void *bl_start = NULL;
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struct bdb_lvds_options *lvds_opts
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= find_section(bdb, BDB_LVDS_OPTIONS);
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dev_priv->lvds_bl = NULL;
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if (lvds_opts)
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p_type = lvds_opts->panel_type;
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else
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return;
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bl_start = find_section(bdb, BDB_LVDS_BACKLIGHT);
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vbt_lvds_bl = (struct bdb_lvds_backlight *)(bl_start + 1) + p_type;
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lvds_bl = kzalloc(sizeof(*vbt_lvds_bl), GFP_KERNEL);
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if (!lvds_bl) {
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dev_err(dev_priv->dev->dev, "out of memory for backlight data\n");
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return;
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}
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memcpy(lvds_bl, vbt_lvds_bl, sizeof(*vbt_lvds_bl));
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dev_priv->lvds_bl = lvds_bl;
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}
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/* Try to find integrated panel data */
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static void parse_lfp_panel_data(struct drm_psb_private *dev_priv,
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struct bdb_header *bdb)
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{
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struct bdb_lvds_options *lvds_options;
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struct bdb_lvds_lfp_data *lvds_lfp_data;
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struct bdb_lvds_lfp_data_entry *entry;
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struct lvds_dvo_timing *dvo_timing;
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struct drm_display_mode *panel_fixed_mode;
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/* Defaults if we can't find VBT info */
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dev_priv->lvds_dither = 0;
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dev_priv->lvds_vbt = 0;
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lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
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if (!lvds_options)
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return;
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dev_priv->lvds_dither = lvds_options->pixel_dither;
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if (lvds_options->panel_type == 0xff)
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return;
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lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
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if (!lvds_lfp_data)
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return;
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entry = &lvds_lfp_data->data[lvds_options->panel_type];
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dvo_timing = &entry->dvo_timing;
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panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode),
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GFP_KERNEL);
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if (panel_fixed_mode == NULL) {
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dev_err(dev_priv->dev->dev, "out of memory for fixed panel mode\n");
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return;
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}
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dev_priv->lvds_vbt = 1;
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fill_detail_timing_data(panel_fixed_mode, dvo_timing);
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if (panel_fixed_mode->htotal > 0 && panel_fixed_mode->vtotal > 0) {
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dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode;
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drm_mode_debug_printmodeline(panel_fixed_mode);
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} else {
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dev_dbg(dev_priv->dev->dev, "ignoring invalid LVDS VBT\n");
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dev_priv->lvds_vbt = 0;
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kfree(panel_fixed_mode);
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}
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return;
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}
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/* Try to find sdvo panel data */
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static void parse_sdvo_panel_data(struct drm_psb_private *dev_priv,
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struct bdb_header *bdb)
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{
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struct bdb_sdvo_lvds_options *sdvo_lvds_options;
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struct lvds_dvo_timing *dvo_timing;
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struct drm_display_mode *panel_fixed_mode;
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dev_priv->sdvo_lvds_vbt_mode = NULL;
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sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
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if (!sdvo_lvds_options)
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return;
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dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS);
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if (!dvo_timing)
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return;
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panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
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if (!panel_fixed_mode)
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return;
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fill_detail_timing_data(panel_fixed_mode,
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dvo_timing + sdvo_lvds_options->panel_type);
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dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode;
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return;
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}
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static void parse_general_features(struct drm_psb_private *dev_priv,
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struct bdb_header *bdb)
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{
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struct bdb_general_features *general;
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/* Set sensible defaults in case we can't find the general block */
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dev_priv->int_tv_support = 1;
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dev_priv->int_crt_support = 1;
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general = find_section(bdb, BDB_GENERAL_FEATURES);
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if (general) {
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dev_priv->int_tv_support = general->int_tv_support;
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dev_priv->int_crt_support = general->int_crt_support;
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dev_priv->lvds_use_ssc = general->enable_ssc;
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if (dev_priv->lvds_use_ssc) {
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dev_priv->lvds_ssc_freq
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= general->ssc_freq ? 100 : 96;
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}
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}
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}
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/**
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* psb_intel_init_bios - initialize VBIOS settings & find VBT
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* @dev: DRM device
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*
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* Loads the Video BIOS and checks that the VBT exists. Sets scratch registers
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* to appropriate values.
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*
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* VBT existence is a sanity check that is relied on by other i830_bios.c code.
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* Note that it would be better to use a BIOS call to get the VBT, as BIOSes may
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* feed an updated VBT back through that, compared to what we'll fetch using
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* this method of groping around in the BIOS data.
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*
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* Returns 0 on success, nonzero on failure.
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*/
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bool psb_intel_init_bios(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct pci_dev *pdev = dev->pdev;
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struct vbt_header *vbt = NULL;
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struct bdb_header *bdb;
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u8 __iomem *bios;
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size_t size;
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int i;
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bios = pci_map_rom(pdev, &size);
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if (!bios)
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return -1;
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/* Scour memory looking for the VBT signature */
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for (i = 0; i + 4 < size; i++) {
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if (!memcmp(bios + i, "$VBT", 4)) {
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vbt = (struct vbt_header *)(bios + i);
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break;
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}
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}
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if (!vbt) {
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dev_err(dev->dev, "VBT signature missing\n");
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pci_unmap_rom(pdev, bios);
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return -1;
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}
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bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);
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/* Grab useful general definitions */
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parse_general_features(dev_priv, bdb);
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parse_lfp_panel_data(dev_priv, bdb);
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parse_sdvo_panel_data(dev_priv, bdb);
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parse_backlight_data(dev_priv, bdb);
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pci_unmap_rom(pdev, bios);
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return 0;
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}
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/**
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* Destroy and free VBT data
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*/
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void psb_intel_destroy_bios(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct drm_display_mode *sdvo_lvds_vbt_mode =
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dev_priv->sdvo_lvds_vbt_mode;
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struct drm_display_mode *lfp_lvds_vbt_mode =
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dev_priv->lfp_lvds_vbt_mode;
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struct bdb_lvds_backlight *lvds_bl =
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dev_priv->lvds_bl;
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/*free sdvo panel mode*/
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if (sdvo_lvds_vbt_mode) {
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dev_priv->sdvo_lvds_vbt_mode = NULL;
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kfree(sdvo_lvds_vbt_mode);
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}
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if (lfp_lvds_vbt_mode) {
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dev_priv->lfp_lvds_vbt_mode = NULL;
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kfree(lfp_lvds_vbt_mode);
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}
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if (lvds_bl) {
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dev_priv->lvds_bl = NULL;
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kfree(lvds_bl);
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}
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}
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@ -0,0 +1,430 @@
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/*
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* Copyright (c) 2006 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef _I830_BIOS_H_
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#define _I830_BIOS_H_
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#include <drm/drmP.h>
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struct vbt_header {
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u8 signature[20]; /**< Always starts with 'VBT$' */
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u16 version; /**< decimal */
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u16 header_size; /**< in bytes */
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u16 vbt_size; /**< in bytes */
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u8 vbt_checksum;
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u8 reserved0;
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u32 bdb_offset; /**< from beginning of VBT */
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u32 aim_offset[4]; /**< from beginning of VBT */
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} __attribute__((packed));
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struct bdb_header {
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u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
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u16 version; /**< decimal */
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u16 header_size; /**< in bytes */
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u16 bdb_size; /**< in bytes */
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};
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/* strictly speaking, this is a "skip" block, but it has interesting info */
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struct vbios_data {
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u8 type; /* 0 == desktop, 1 == mobile */
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u8 relstage;
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u8 chipset;
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u8 lvds_present:1;
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u8 tv_present:1;
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u8 rsvd2:6; /* finish byte */
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u8 rsvd3[4];
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u8 signon[155];
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u8 copyright[61];
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u16 code_segment;
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u8 dos_boot_mode;
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u8 bandwidth_percent;
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u8 rsvd4; /* popup memory size */
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u8 resize_pci_bios;
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u8 rsvd5; /* is crt already on ddc2 */
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} __attribute__((packed));
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/*
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* There are several types of BIOS data blocks (BDBs), each block has
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* an ID and size in the first 3 bytes (ID in first, size in next 2).
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* Known types are listed below.
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*/
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#define BDB_GENERAL_FEATURES 1
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#define BDB_GENERAL_DEFINITIONS 2
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#define BDB_OLD_TOGGLE_LIST 3
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#define BDB_MODE_SUPPORT_LIST 4
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#define BDB_GENERIC_MODE_TABLE 5
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#define BDB_EXT_MMIO_REGS 6
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#define BDB_SWF_IO 7
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#define BDB_SWF_MMIO 8
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#define BDB_DOT_CLOCK_TABLE 9
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#define BDB_MODE_REMOVAL_TABLE 10
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#define BDB_CHILD_DEVICE_TABLE 11
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#define BDB_DRIVER_FEATURES 12
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#define BDB_DRIVER_PERSISTENCE 13
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#define BDB_EXT_TABLE_PTRS 14
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#define BDB_DOT_CLOCK_OVERRIDE 15
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#define BDB_DISPLAY_SELECT 16
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/* 17 rsvd */
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#define BDB_DRIVER_ROTATION 18
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#define BDB_DISPLAY_REMOVE 19
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#define BDB_OEM_CUSTOM 20
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#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
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#define BDB_SDVO_LVDS_OPTIONS 22
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#define BDB_SDVO_PANEL_DTDS 23
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#define BDB_SDVO_LVDS_PNP_IDS 24
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#define BDB_SDVO_LVDS_POWER_SEQ 25
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#define BDB_TV_OPTIONS 26
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#define BDB_LVDS_OPTIONS 40
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#define BDB_LVDS_LFP_DATA_PTRS 41
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#define BDB_LVDS_LFP_DATA 42
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#define BDB_LVDS_BACKLIGHT 43
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#define BDB_LVDS_POWER 44
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#define BDB_SKIP 254 /* VBIOS private block, ignore */
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struct bdb_general_features {
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/* bits 1 */
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u8 panel_fitting:2;
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u8 flexaim:1;
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u8 msg_enable:1;
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u8 clear_screen:3;
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u8 color_flip:1;
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/* bits 2 */
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u8 download_ext_vbt:1;
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u8 enable_ssc:1;
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u8 ssc_freq:1;
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u8 enable_lfp_on_override:1;
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u8 disable_ssc_ddt:1;
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u8 rsvd8:3; /* finish byte */
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/* bits 3 */
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u8 disable_smooth_vision:1;
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u8 single_dvi:1;
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u8 rsvd9:6; /* finish byte */
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/* bits 4 */
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u8 legacy_monitor_detect;
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/* bits 5 */
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u8 int_crt_support:1;
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u8 int_tv_support:1;
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u8 rsvd11:6; /* finish byte */
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} __attribute__((packed));
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struct bdb_general_definitions {
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/* DDC GPIO */
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u8 crt_ddc_gmbus_pin;
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/* DPMS bits */
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u8 dpms_acpi:1;
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u8 skip_boot_crt_detect:1;
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u8 dpms_aim:1;
|
||||
u8 rsvd1:5; /* finish byte */
|
||||
|
||||
/* boot device bits */
|
||||
u8 boot_display[2];
|
||||
u8 child_dev_size;
|
||||
|
||||
/* device info */
|
||||
u8 tv_or_lvds_info[33];
|
||||
u8 dev1[33];
|
||||
u8 dev2[33];
|
||||
u8 dev3[33];
|
||||
u8 dev4[33];
|
||||
/* may be another device block here on some platforms */
|
||||
};
|
||||
|
||||
struct bdb_lvds_options {
|
||||
u8 panel_type;
|
||||
u8 rsvd1;
|
||||
/* LVDS capabilities, stored in a dword */
|
||||
u8 pfit_mode:2;
|
||||
u8 pfit_text_mode_enhanced:1;
|
||||
u8 pfit_gfx_mode_enhanced:1;
|
||||
u8 pfit_ratio_auto:1;
|
||||
u8 pixel_dither:1;
|
||||
u8 lvds_edid:1;
|
||||
u8 rsvd2:1;
|
||||
u8 rsvd4;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_backlight {
|
||||
u8 type:2;
|
||||
u8 pol:1;
|
||||
u8 gpio:3;
|
||||
u8 gmbus:2;
|
||||
u16 freq;
|
||||
u8 minbrightness;
|
||||
u8 i2caddr;
|
||||
u8 brightnesscmd;
|
||||
/*FIXME: more...*/
|
||||
} __attribute__((packed));
|
||||
|
||||
/* LFP pointer table contains entries to the struct below */
|
||||
struct bdb_lvds_lfp_data_ptr {
|
||||
u16 fp_timing_offset; /* offsets are from start of bdb */
|
||||
u8 fp_table_size;
|
||||
u16 dvo_timing_offset;
|
||||
u8 dvo_table_size;
|
||||
u16 panel_pnp_id_offset;
|
||||
u8 pnp_table_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data_ptrs {
|
||||
u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
|
||||
struct bdb_lvds_lfp_data_ptr ptr[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
/* LFP data has 3 blocks per entry */
|
||||
struct lvds_fp_timing {
|
||||
u16 x_res;
|
||||
u16 y_res;
|
||||
u32 lvds_reg;
|
||||
u32 lvds_reg_val;
|
||||
u32 pp_on_reg;
|
||||
u32 pp_on_reg_val;
|
||||
u32 pp_off_reg;
|
||||
u32 pp_off_reg_val;
|
||||
u32 pp_cycle_reg;
|
||||
u32 pp_cycle_reg_val;
|
||||
u32 pfit_reg;
|
||||
u32 pfit_reg_val;
|
||||
u16 terminator;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct lvds_dvo_timing {
|
||||
u16 clock; /**< In 10khz */
|
||||
u8 hactive_lo;
|
||||
u8 hblank_lo;
|
||||
u8 hblank_hi:4;
|
||||
u8 hactive_hi:4;
|
||||
u8 vactive_lo;
|
||||
u8 vblank_lo;
|
||||
u8 vblank_hi:4;
|
||||
u8 vactive_hi:4;
|
||||
u8 hsync_off_lo;
|
||||
u8 hsync_pulse_width;
|
||||
u8 vsync_pulse_width:4;
|
||||
u8 vsync_off:4;
|
||||
u8 rsvd0:6;
|
||||
u8 hsync_off_hi:2;
|
||||
u8 h_image;
|
||||
u8 v_image;
|
||||
u8 max_hv;
|
||||
u8 h_border;
|
||||
u8 v_border;
|
||||
u8 rsvd1:3;
|
||||
u8 digital:2;
|
||||
u8 vsync_positive:1;
|
||||
u8 hsync_positive:1;
|
||||
u8 rsvd2:1;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct lvds_pnp_id {
|
||||
u16 mfg_name;
|
||||
u16 product_code;
|
||||
u32 serial;
|
||||
u8 mfg_week;
|
||||
u8 mfg_year;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data_entry {
|
||||
struct lvds_fp_timing fp_timing;
|
||||
struct lvds_dvo_timing dvo_timing;
|
||||
struct lvds_pnp_id pnp_id;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_lvds_lfp_data {
|
||||
struct bdb_lvds_lfp_data_entry data[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct aimdb_header {
|
||||
char signature[16];
|
||||
char oem_device[20];
|
||||
u16 aimdb_version;
|
||||
u16 aimdb_header_size;
|
||||
u16 aimdb_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct aimdb_block {
|
||||
u8 aimdb_id;
|
||||
u16 aimdb_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct vch_panel_data {
|
||||
u16 fp_timing_offset;
|
||||
u8 fp_timing_size;
|
||||
u16 dvo_timing_offset;
|
||||
u8 dvo_timing_size;
|
||||
u16 text_fitting_offset;
|
||||
u8 text_fitting_size;
|
||||
u16 graphics_fitting_offset;
|
||||
u8 graphics_fitting_size;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct vch_bdb_22 {
|
||||
struct aimdb_block aimdb_block;
|
||||
struct vch_panel_data panels[16];
|
||||
} __attribute__((packed));
|
||||
|
||||
struct bdb_sdvo_lvds_options {
|
||||
u8 panel_backlight;
|
||||
u8 h40_set_panel_type;
|
||||
u8 panel_type;
|
||||
u8 ssc_clk_freq;
|
||||
u16 als_low_trip;
|
||||
u16 als_high_trip;
|
||||
u8 sclalarcoeff_tab_row_num;
|
||||
u8 sclalarcoeff_tab_row_size;
|
||||
u8 coefficient[8];
|
||||
u8 panel_misc_bits_1;
|
||||
u8 panel_misc_bits_2;
|
||||
u8 panel_misc_bits_3;
|
||||
u8 panel_misc_bits_4;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
extern bool psb_intel_init_bios(struct drm_device *dev);
|
||||
extern void psb_intel_destroy_bios(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* Driver<->VBIOS interaction occurs through scratch bits in
|
||||
* GR18 & SWF*.
|
||||
*/
|
||||
|
||||
/* GR18 bits are set on display switch and hotkey events */
|
||||
#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
|
||||
#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
|
||||
#define GR18_HK_NONE (0x0<<3)
|
||||
#define GR18_HK_LFP_STRETCH (0x1<<3)
|
||||
#define GR18_HK_TOGGLE_DISP (0x2<<3)
|
||||
#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
|
||||
#define GR18_HK_POPUP_DISABLED (0x6<<3)
|
||||
#define GR18_HK_POPUP_ENABLED (0x7<<3)
|
||||
#define GR18_HK_PFIT (0x8<<3)
|
||||
#define GR18_HK_APM_CHANGE (0xa<<3)
|
||||
#define GR18_HK_MULTIPLE (0xc<<3)
|
||||
#define GR18_USER_INT_EN (1<<2)
|
||||
#define GR18_A0000_FLUSH_EN (1<<1)
|
||||
#define GR18_SMM_EN (1<<0)
|
||||
|
||||
/* Set by driver, cleared by VBIOS */
|
||||
#define SWF00_YRES_SHIFT 16
|
||||
#define SWF00_XRES_SHIFT 0
|
||||
#define SWF00_RES_MASK 0xffff
|
||||
|
||||
/* Set by VBIOS at boot time and driver at runtime */
|
||||
#define SWF01_TV2_FORMAT_SHIFT 8
|
||||
#define SWF01_TV1_FORMAT_SHIFT 0
|
||||
#define SWF01_TV_FORMAT_MASK 0xffff
|
||||
|
||||
#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
|
||||
#define SWF10_GTT_OVERRIDE_EN (1<<28)
|
||||
#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
|
||||
#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
|
||||
#define SWF10_OLD_TOGGLE 0x0
|
||||
#define SWF10_TOGGLE_LIST_1 0x1
|
||||
#define SWF10_TOGGLE_LIST_2 0x2
|
||||
#define SWF10_TOGGLE_LIST_3 0x3
|
||||
#define SWF10_TOGGLE_LIST_4 0x4
|
||||
#define SWF10_PANNING_EN (1<<23)
|
||||
#define SWF10_DRIVER_LOADED (1<<22)
|
||||
#define SWF10_EXTENDED_DESKTOP (1<<21)
|
||||
#define SWF10_EXCLUSIVE_MODE (1<<20)
|
||||
#define SWF10_OVERLAY_EN (1<<19)
|
||||
#define SWF10_PLANEB_HOLDOFF (1<<18)
|
||||
#define SWF10_PLANEA_HOLDOFF (1<<17)
|
||||
#define SWF10_VGA_HOLDOFF (1<<16)
|
||||
#define SWF10_ACTIVE_DISP_MASK 0xffff
|
||||
#define SWF10_PIPEB_LFP2 (1<<15)
|
||||
#define SWF10_PIPEB_EFP2 (1<<14)
|
||||
#define SWF10_PIPEB_TV2 (1<<13)
|
||||
#define SWF10_PIPEB_CRT2 (1<<12)
|
||||
#define SWF10_PIPEB_LFP (1<<11)
|
||||
#define SWF10_PIPEB_EFP (1<<10)
|
||||
#define SWF10_PIPEB_TV (1<<9)
|
||||
#define SWF10_PIPEB_CRT (1<<8)
|
||||
#define SWF10_PIPEA_LFP2 (1<<7)
|
||||
#define SWF10_PIPEA_EFP2 (1<<6)
|
||||
#define SWF10_PIPEA_TV2 (1<<5)
|
||||
#define SWF10_PIPEA_CRT2 (1<<4)
|
||||
#define SWF10_PIPEA_LFP (1<<3)
|
||||
#define SWF10_PIPEA_EFP (1<<2)
|
||||
#define SWF10_PIPEA_TV (1<<1)
|
||||
#define SWF10_PIPEA_CRT (1<<0)
|
||||
|
||||
#define SWF11_MEMORY_SIZE_SHIFT 16
|
||||
#define SWF11_SV_TEST_EN (1<<15)
|
||||
#define SWF11_IS_AGP (1<<14)
|
||||
#define SWF11_DISPLAY_HOLDOFF (1<<13)
|
||||
#define SWF11_DPMS_REDUCED (1<<12)
|
||||
#define SWF11_IS_VBE_MODE (1<<11)
|
||||
#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
|
||||
#define SWF11_DPMS_MASK 0x07
|
||||
#define SWF11_DPMS_OFF (1<<2)
|
||||
#define SWF11_DPMS_SUSPEND (1<<1)
|
||||
#define SWF11_DPMS_STANDBY (1<<0)
|
||||
#define SWF11_DPMS_ON 0
|
||||
|
||||
#define SWF14_GFX_PFIT_EN (1<<31)
|
||||
#define SWF14_TEXT_PFIT_EN (1<<30)
|
||||
#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
|
||||
#define SWF14_POPUP_EN (1<<28)
|
||||
#define SWF14_DISPLAY_HOLDOFF (1<<27)
|
||||
#define SWF14_DISP_DETECT_EN (1<<26)
|
||||
#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
|
||||
#define SWF14_DRIVER_STATUS (1<<24)
|
||||
#define SWF14_OS_TYPE_WIN9X (1<<23)
|
||||
#define SWF14_OS_TYPE_WINNT (1<<22)
|
||||
/* 21:19 rsvd */
|
||||
#define SWF14_PM_TYPE_MASK 0x00070000
|
||||
#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
|
||||
#define SWF14_PM_ACPI (0x3 << 16)
|
||||
#define SWF14_PM_APM_12 (0x2 << 16)
|
||||
#define SWF14_PM_APM_11 (0x1 << 16)
|
||||
#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
|
||||
/* if GR18 indicates a display switch */
|
||||
#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
|
||||
#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
|
||||
#define SWF14_DS_PIPEB_TV2_EN (1<<13)
|
||||
#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
|
||||
#define SWF14_DS_PIPEB_LFP_EN (1<<11)
|
||||
#define SWF14_DS_PIPEB_EFP_EN (1<<10)
|
||||
#define SWF14_DS_PIPEB_TV_EN (1<<9)
|
||||
#define SWF14_DS_PIPEB_CRT_EN (1<<8)
|
||||
#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
|
||||
#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
|
||||
#define SWF14_DS_PIPEA_TV2_EN (1<<5)
|
||||
#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
|
||||
#define SWF14_DS_PIPEA_LFP_EN (1<<3)
|
||||
#define SWF14_DS_PIPEA_EFP_EN (1<<2)
|
||||
#define SWF14_DS_PIPEA_TV_EN (1<<1)
|
||||
#define SWF14_DS_PIPEA_CRT_EN (1<<0)
|
||||
/* if GR18 indicates a panel fitting request */
|
||||
#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
|
||||
/* if GR18 indicates an APM change request */
|
||||
#define SWF14_APM_HIBERNATE 0x4
|
||||
#define SWF14_APM_SUSPEND 0x3
|
||||
#define SWF14_APM_STANDBY 0x1
|
||||
#define SWF14_APM_RESTORE 0x0
|
||||
|
||||
#endif /* _I830_BIOS_H_ */
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright 2010 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "psb_drv.h"
|
||||
|
||||
struct opregion_header {
|
||||
u8 signature[16];
|
||||
u32 size;
|
||||
u32 opregion_ver;
|
||||
u8 bios_ver[32];
|
||||
u8 vbios_ver[16];
|
||||
u8 driver_ver[16];
|
||||
u32 mboxes;
|
||||
u8 reserved[164];
|
||||
} __packed;
|
||||
|
||||
struct opregion_apci {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
struct opregion_swsci {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
struct opregion_acpi {
|
||||
/*FIXME: add it later*/
|
||||
} __packed;
|
||||
|
||||
int gma_intel_opregion_init(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
u32 opregion_phy;
|
||||
void *base;
|
||||
u32 *lid_state;
|
||||
|
||||
dev_priv->lid_state = NULL;
|
||||
|
||||
pci_read_config_dword(dev->pdev, 0xfc, &opregion_phy);
|
||||
if (opregion_phy == 0)
|
||||
return -ENOTSUPP;
|
||||
|
||||
base = ioremap(opregion_phy, 8*1024);
|
||||
if (!base)
|
||||
return -ENOMEM;
|
||||
|
||||
lid_state = base + 0x01ac;
|
||||
|
||||
dev_priv->lid_state = lid_state;
|
||||
dev_priv->lid_last_state = readl(lid_state);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int gma_intel_opregion_exit(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
if (dev_priv->lid_state)
|
||||
iounmap(dev_priv->lid_state);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/* TODO
|
||||
* - Split functions by vbt type
|
||||
* - Make them all take drm_device
|
||||
* - Check ioremap failures
|
||||
*/
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
#include "psb_drm.h"
|
||||
#include "psb_drv.h"
|
||||
#include "mid_bios.h"
|
||||
|
||||
static void mid_get_fuse_settings(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
|
||||
uint32_t fuse_value = 0;
|
||||
uint32_t fuse_value_tmp = 0;
|
||||
|
||||
#define FB_REG06 0xD0810600
|
||||
#define FB_MIPI_DISABLE (1 << 11)
|
||||
#define FB_REG09 0xD0810900
|
||||
#define FB_REG09 0xD0810900
|
||||
#define FB_SKU_MASK 0x7000
|
||||
#define FB_SKU_SHIFT 12
|
||||
#define FB_SKU_100 0
|
||||
#define FB_SKU_100L 1
|
||||
#define FB_SKU_83 2
|
||||
pci_write_config_dword(pci_root, 0xD0, FB_REG06);
|
||||
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
|
||||
|
||||
/* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
|
||||
if (IS_MRST(dev))
|
||||
dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
|
||||
|
||||
DRM_INFO("internal display is %s\n",
|
||||
dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
|
||||
|
||||
/* Prevent runtime suspend at start*/
|
||||
if (dev_priv->iLVDS_enable) {
|
||||
dev_priv->is_lvds_on = true;
|
||||
dev_priv->is_mipi_on = false;
|
||||
} else {
|
||||
dev_priv->is_mipi_on = true;
|
||||
dev_priv->is_lvds_on = false;
|
||||
}
|
||||
|
||||
dev_priv->video_device_fuse = fuse_value;
|
||||
|
||||
pci_write_config_dword(pci_root, 0xD0, FB_REG09);
|
||||
pci_read_config_dword(pci_root, 0xD4, &fuse_value);
|
||||
|
||||
dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
|
||||
fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
|
||||
|
||||
dev_priv->fuse_reg_value = fuse_value;
|
||||
|
||||
switch (fuse_value_tmp) {
|
||||
case FB_SKU_100:
|
||||
dev_priv->core_freq = 200;
|
||||
break;
|
||||
case FB_SKU_100L:
|
||||
dev_priv->core_freq = 100;
|
||||
break;
|
||||
case FB_SKU_83:
|
||||
dev_priv->core_freq = 166;
|
||||
break;
|
||||
default:
|
||||
dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
|
||||
fuse_value_tmp);
|
||||
dev_priv->core_freq = 0;
|
||||
}
|
||||
dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
|
||||
pci_dev_put(pci_root);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the revison ID, B0:D2:F0;0x08
|
||||
*/
|
||||
static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
uint32_t platform_rev_id = 0;
|
||||
struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
|
||||
|
||||
pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
|
||||
dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
|
||||
pci_dev_put(pci_gfx_root);
|
||||
dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
|
||||
dev_priv->platform_rev_id);
|
||||
}
|
||||
|
||||
static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
|
||||
{
|
||||
struct drm_device *dev = dev_priv->dev;
|
||||
struct oaktrail_vbt *vbt = &dev_priv->vbt_data;
|
||||
u32 addr;
|
||||
u16 new_size;
|
||||
u8 *vbt_virtual;
|
||||
u8 bpi;
|
||||
u8 number_desc = 0;
|
||||
struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
|
||||
struct gct_r10_timing_info ti;
|
||||
void *pGCT;
|
||||
struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
|
||||
|
||||
/* Get the address of the platform config vbt, B0:D2:F0;0xFC */
|
||||
pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
|
||||
pci_dev_put(pci_gfx_root);
|
||||
|
||||
dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
|
||||
|
||||
/* check for platform config address == 0. */
|
||||
/* this means fw doesn't support vbt */
|
||||
|
||||
if (addr == 0) {
|
||||
vbt->size = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* get the virtual address of the vbt */
|
||||
vbt_virtual = ioremap(addr, sizeof(*vbt));
|
||||
|
||||
memcpy(vbt, vbt_virtual, sizeof(*vbt));
|
||||
iounmap(vbt_virtual); /* Free virtual address space */
|
||||
|
||||
dev_dbg(dev->dev, "GCT revision is %x\n", vbt->revision);
|
||||
|
||||
switch (vbt->revision) {
|
||||
case 0:
|
||||
vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
|
||||
vbt->size - sizeof(*vbt) + 4);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
bpi = ((struct oaktrail_gct_v1 *)pGCT)->PD.BootPanelIndex;
|
||||
dev_priv->gct_data.bpi = bpi;
|
||||
dev_priv->gct_data.pt =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->PD.PanelType;
|
||||
memcpy(&dev_priv->gct_data.DTD,
|
||||
&((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].DTD,
|
||||
sizeof(struct oaktrail_timing_info));
|
||||
dev_priv->gct_data.Panel_Port_Control =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
((struct oaktrail_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
|
||||
break;
|
||||
case 1:
|
||||
vbt->oaktrail_gct = ioremap(addr + sizeof(*vbt) - 4,
|
||||
vbt->size - sizeof(*vbt) + 4);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
bpi = ((struct oaktrail_gct_v2 *)pGCT)->PD.BootPanelIndex;
|
||||
dev_priv->gct_data.bpi = bpi;
|
||||
dev_priv->gct_data.pt =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->PD.PanelType;
|
||||
memcpy(&dev_priv->gct_data.DTD,
|
||||
&((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].DTD,
|
||||
sizeof(struct oaktrail_timing_info));
|
||||
dev_priv->gct_data.Panel_Port_Control =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
((struct oaktrail_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
|
||||
break;
|
||||
case 0x10:
|
||||
/*header definition changed from rev 01 (v2) to rev 10h. */
|
||||
/*so, some values have changed location*/
|
||||
new_size = vbt->checksum; /*checksum contains lo size byte*/
|
||||
/*LSB of oaktrail_gct contains hi size byte*/
|
||||
new_size |= ((0xff & (unsigned int)vbt->oaktrail_gct)) << 8;
|
||||
|
||||
vbt->checksum = vbt->size; /*size contains the checksum*/
|
||||
if (new_size > 0xff)
|
||||
vbt->size = 0xff; /*restrict size to 255*/
|
||||
else
|
||||
vbt->size = new_size;
|
||||
|
||||
/* number of descriptors defined in the GCT */
|
||||
number_desc = ((0xff00 & (unsigned int)vbt->oaktrail_gct)) >> 8;
|
||||
bpi = ((0xff0000 & (unsigned int)vbt->oaktrail_gct)) >> 16;
|
||||
vbt->oaktrail_gct = ioremap(addr + GCT_R10_HEADER_SIZE,
|
||||
GCT_R10_DISPLAY_DESC_SIZE * number_desc);
|
||||
pGCT = vbt->oaktrail_gct;
|
||||
pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
|
||||
dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
|
||||
|
||||
/*copy the GCT display timings into a temp structure*/
|
||||
memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
|
||||
|
||||
/*now copy the temp struct into the dev_priv->gct_data*/
|
||||
dp_ti->pixel_clock = ti.pixel_clock;
|
||||
dp_ti->hactive_hi = ti.hactive_hi;
|
||||
dp_ti->hactive_lo = ti.hactive_lo;
|
||||
dp_ti->hblank_hi = ti.hblank_hi;
|
||||
dp_ti->hblank_lo = ti.hblank_lo;
|
||||
dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
|
||||
dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
|
||||
dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
|
||||
dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
|
||||
dp_ti->vactive_hi = ti.vactive_hi;
|
||||
dp_ti->vactive_lo = ti.vactive_lo;
|
||||
dp_ti->vblank_hi = ti.vblank_hi;
|
||||
dp_ti->vblank_lo = ti.vblank_lo;
|
||||
dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
|
||||
dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
|
||||
dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
|
||||
dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
|
||||
|
||||
/* Move the MIPI_Display_Descriptor data from GCT to dev priv */
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
|
||||
*((u8 *)pGCT + 0x0d);
|
||||
dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
|
||||
(*((u8 *)pGCT + 0x0e)) << 8;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "Unknown revision of GCT!\n");
|
||||
vbt->size = 0;
|
||||
}
|
||||
}
|
||||
|
||||
int mid_chip_setup(struct drm_device *dev)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
mid_get_fuse_settings(dev);
|
||||
mid_get_vbt_data(dev_priv);
|
||||
mid_get_pci_revID(dev_priv);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/**************************************************************************
|
||||
* Copyright (c) 2011, Intel Corporation.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
extern int mid_chip_setup(struct drm_device *dev);
|
||||
|
||||
Loading…
Reference in New Issue