staging: dwc2: unshift non-bool register value constants
Various register fields wider than one bit have constants defined for their value. Previously, these registers would define the values as they appear in the register, so shifted to the right to the position the value appears in the register. This commit changes those constants to their natural values (e.g, 0, 1, 2, etc.), as they are after shifting the register value to the right. This also changes all relevant code to shift the values before comparing them with constants. This has the advantage that the values can be stored in smaller variables (now they always require a u32) and makes the handling of these values more consistent with other register fields that represent natural numbers instead of enumerations (e.g., number of host channels). Signed-off-by: Matthijs Kooijman <matthijs@stdin.nl> Acked-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>hifive-unleashed-5.1
Matthijs Kooijman
Greg Kroah-Hartman
parent
3b9edf8847
commit
f923463335
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@ -90,8 +90,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
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*/
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static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
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{
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u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
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u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
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u32 hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
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GHWCFG2_HS_PHY_TYPE_SHIFT;
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u32 fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
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GHWCFG2_FS_PHY_TYPE_SHIFT;
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u32 hcfg, val;
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if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
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@ -108,7 +110,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
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dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
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hcfg = readl(hsotg->regs + HCFG);
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hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
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hcfg |= val;
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hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
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writel(hcfg, hsotg->regs + HCFG);
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}
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@ -256,8 +258,10 @@ static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
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dwc2_hs_phy_init(hsotg, select_phy);
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}
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hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
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fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
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hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
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GHWCFG2_HS_PHY_TYPE_SHIFT;
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fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
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GHWCFG2_FS_PHY_TYPE_SHIFT;
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if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
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fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
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@ -279,7 +283,8 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
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{
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u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
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switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
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switch ((hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
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GHWCFG2_ARCHITECTURE_SHIFT) {
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case GHWCFG2_EXT_DMA_ARCH:
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dev_err(hsotg->dev, "External DMA Mode not supported\n");
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return -EINVAL;
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@ -328,7 +333,8 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
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usbcfg = readl(hsotg->regs + GUSBCFG);
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usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
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switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
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switch ((hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
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GHWCFG2_OP_MODE_SHIFT) {
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case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
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if (hsotg->core_params->otg_cap ==
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DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
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@ -599,7 +605,8 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
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}
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if (hsotg->core_params->dma_desc_enable > 0) {
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u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
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u32 op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
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GHWCFG2_OP_MODE_SHIFT;
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if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
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!(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
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@ -1666,7 +1673,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
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if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
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!(usbcfg & GUSBCFG_PHYIF16))
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clock = 60;
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if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
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if ((usbcfg & GUSBCFG_PHYSEL) &&
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(hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
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GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
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clock = 48;
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if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
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@ -1679,14 +1687,15 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
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!(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
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clock = 48;
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if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
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(hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
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(hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
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GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
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clock = 48;
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if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
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if ((usbcfg & GUSBCFG_PHYSEL) &&
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(hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
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GHWCFG2_FS_PHY_TYPE_DEDICATED)
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clock = 48;
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if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)
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if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
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/* High speed case */
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return 125 * clock;
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else
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@ -1957,7 +1966,8 @@ int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
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int retval = 0;
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u32 op_mode;
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op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
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op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
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GHWCFG2_OP_MODE_SHIFT;
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switch (val) {
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case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
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@ -2015,8 +2025,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
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int valid = 1;
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int retval = 0;
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if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==
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GHWCFG2_SLAVE_ONLY_ARCH)
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if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
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GHWCFG2_ARCHITECTURE_SHIFT == GHWCFG2_SLAVE_ONLY_ARCH)
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valid = 0;
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if (val < 0)
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valid = 0;
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@ -2026,8 +2036,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
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dev_err(hsotg->dev,
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"%d invalid for dma_enable parameter. Check HW configuration.\n",
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val);
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val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=
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GHWCFG2_SLAVE_ONLY_ARCH;
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val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
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GHWCFG2_ARCHITECTURE_SHIFT != GHWCFG2_SLAVE_ONLY_ARCH;
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dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
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retval = -EINVAL;
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}
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@ -2276,8 +2286,10 @@ int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
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}
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#ifndef NO_FS_PHY_HW_CHECKS
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hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
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fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
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hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
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GHWCFG2_HS_PHY_TYPE_SHIFT;
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fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
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GHWCFG2_FS_PHY_TYPE_SHIFT;
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if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
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(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
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@ -2588,7 +2600,8 @@ int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
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if (val != -1)
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hsotg->core_params->ahbcfg = val;
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else
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hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4;
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hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
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GAHBCFG_HBSTLEN_SHIFT;
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return 0;
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}
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@ -1612,7 +1612,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
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if (hprt0 & HPRT0_PWR)
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port_status |= USB_PORT_STAT_POWER;
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speed = hprt0 & HPRT0_SPD_MASK;
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speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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if (speed == HPRT0_SPD_HIGH_SPEED)
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port_status |= USB_PORT_STAT_HIGH_SPEED;
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else if (speed == HPRT0_SPD_LOW_SPEED)
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@ -122,11 +122,11 @@ struct dwc2_host_chan {
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unsigned ep_type:2;
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unsigned max_packet:11;
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unsigned data_pid_start:2;
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#define DWC2_HC_PID_DATA0 (TSIZ_SC_MC_PID_DATA0 >> TSIZ_SC_MC_PID_SHIFT)
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#define DWC2_HC_PID_DATA2 (TSIZ_SC_MC_PID_DATA2 >> TSIZ_SC_MC_PID_SHIFT)
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#define DWC2_HC_PID_DATA1 (TSIZ_SC_MC_PID_DATA1 >> TSIZ_SC_MC_PID_SHIFT)
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#define DWC2_HC_PID_MDATA (TSIZ_SC_MC_PID_MDATA >> TSIZ_SC_MC_PID_SHIFT)
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#define DWC2_HC_PID_SETUP (TSIZ_SC_MC_PID_SETUP >> TSIZ_SC_MC_PID_SHIFT)
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#define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
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#define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
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#define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
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#define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
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#define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
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unsigned multi_count:2;
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@ -146,10 +146,10 @@ struct dwc2_host_chan {
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u8 hub_addr;
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u8 hub_port;
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u8 xact_pos;
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#define DWC2_HCSPLT_XACTPOS_MID (HCSPLT_XACTPOS_MID >> HCSPLT_XACTPOS_SHIFT)
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#define DWC2_HCSPLT_XACTPOS_END (HCSPLT_XACTPOS_END >> HCSPLT_XACTPOS_SHIFT)
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#define DWC2_HCSPLT_XACTPOS_BEGIN (HCSPLT_XACTPOS_BEGIN >> HCSPLT_XACTPOS_SHIFT)
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#define DWC2_HCSPLT_XACTPOS_ALL (HCSPLT_XACTPOS_ALL >> HCSPLT_XACTPOS_SHIFT)
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#define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
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#define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
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#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
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#define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
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u8 requests;
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u8 schinfo;
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@ -177,7 +177,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
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GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT;
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dpid = grxsts >> GRXSTS_DPID_SHIFT &
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GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT;
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pktsts = grxsts & GRXSTS_PKTSTS_MASK;
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pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
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/* Packet Status */
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if (dbg_perio()) {
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@ -185,9 +185,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
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dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
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dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
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chan->data_pid_start);
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dev_vdbg(hsotg->dev, " PStatus = %d\n",
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pktsts >> GRXSTS_PKTSTS_SHIFT &
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GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);
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dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
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}
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switch (pktsts) {
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@ -266,7 +264,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
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}
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usbcfg = readl(hsotg->regs + GUSBCFG);
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prtspd = hprt0 & HPRT0_SPD_MASK;
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prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
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/* Low power */
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@ -278,7 +276,8 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
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}
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hcfg = readl(hsotg->regs + HCFG);
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fslspclksel = hcfg & HCFG_FSLSPCLKSEL_MASK;
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fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
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HCFG_FSLSPCLKSEL_SHIFT;
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if (prtspd == HPRT0_SPD_LOW_SPEED &&
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params->host_ls_low_power_phy_clk ==
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@ -287,8 +286,9 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
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dev_vdbg(hsotg->dev,
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"FS_PHY programming HCFG to 6 MHz\n");
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if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
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fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
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hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
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hcfg |= HCFG_FSLSPCLKSEL_6_MHZ;
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hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
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writel(hcfg, hsotg->regs + HCFG);
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do_reset = 1;
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}
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@ -297,8 +297,9 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
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dev_vdbg(hsotg->dev,
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"FS_PHY programming HCFG to 48 MHz\n");
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if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
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fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
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hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
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hcfg |= HCFG_FSLSPCLKSEL_48_MHZ;
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hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
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writel(hcfg, hsotg->regs + HCFG);
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do_reset = 1;
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}
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@ -515,7 +516,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
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struct dwc2_qtd *qtd)
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{
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u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
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u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK;
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u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
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if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
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if (pid == TSIZ_SC_MC_PID_DATA0)
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@ -116,7 +116,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
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qh->interval = 8;
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#endif
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hprt = readl(hsotg->regs + HPRT0);
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prtspd = hprt & HPRT0_SPD_MASK;
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prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
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if (prtspd == HPRT0_SPD_HIGH_SPEED &&
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(dev_speed == USB_SPEED_LOW ||
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dev_speed == USB_SPEED_FULL)) {
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@ -72,11 +72,11 @@
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#define GAHBCFG_DMA_EN (1 << 5)
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#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
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#define GAHBCFG_HBSTLEN_SHIFT 1
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#define GAHBCFG_HBSTLEN_SINGLE (0 << 1)
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#define GAHBCFG_HBSTLEN_INCR (1 << 1)
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#define GAHBCFG_HBSTLEN_INCR4 (3 << 1)
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#define GAHBCFG_HBSTLEN_INCR8 (5 << 1)
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#define GAHBCFG_HBSTLEN_INCR16 (7 << 1)
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#define GAHBCFG_HBSTLEN_SINGLE 0
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#define GAHBCFG_HBSTLEN_INCR 1
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#define GAHBCFG_HBSTLEN_INCR4 3
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#define GAHBCFG_HBSTLEN_INCR8 5
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#define GAHBCFG_HBSTLEN_INCR16 7
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#define GAHBCFG_GLBL_INTR_EN (1 << 0)
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#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
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GAHBCFG_NP_TXF_EMP_LVL | \
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@ -169,15 +169,15 @@
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#define GRXSTS_FN_SHIFT 25
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#define GRXSTS_PKTSTS_MASK (0xf << 17)
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#define GRXSTS_PKTSTS_SHIFT 17
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#define GRXSTS_PKTSTS_GLOBALOUTNAK (1 << 17)
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#define GRXSTS_PKTSTS_OUTRX (2 << 17)
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#define GRXSTS_PKTSTS_HCHIN (2 << 17)
|
||||
#define GRXSTS_PKTSTS_OUTDONE (3 << 17)
|
||||
#define GRXSTS_PKTSTS_HCHIN_XFER_COMP (3 << 17)
|
||||
#define GRXSTS_PKTSTS_SETUPDONE (4 << 17)
|
||||
#define GRXSTS_PKTSTS_DATATOGGLEERR (5 << 17)
|
||||
#define GRXSTS_PKTSTS_SETUPRX (6 << 17)
|
||||
#define GRXSTS_PKTSTS_HCHHALTED (7 << 17)
|
||||
#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
|
||||
#define GRXSTS_PKTSTS_OUTRX 2
|
||||
#define GRXSTS_PKTSTS_HCHIN 2
|
||||
#define GRXSTS_PKTSTS_OUTDONE 3
|
||||
#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
|
||||
#define GRXSTS_PKTSTS_SETUPDONE 4
|
||||
#define GRXSTS_PKTSTS_DATATOGGLEERR 5
|
||||
#define GRXSTS_PKTSTS_SETUPRX 6
|
||||
#define GRXSTS_PKTSTS_HCHHALTED 7
|
||||
#define GRXSTS_HCHNUM_MASK (0xf << 0)
|
||||
#define GRXSTS_HCHNUM_SHIFT 0
|
||||
#define GRXSTS_DPID_MASK (0x3 << 15)
|
||||
|
|
@ -241,32 +241,32 @@
|
|||
#define GHWCFG2_NUM_DEV_EP_SHIFT 10
|
||||
#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
|
||||
#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
|
||||
#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED (0 << 8)
|
||||
#define GHWCFG2_FS_PHY_TYPE_DEDICATED (1 << 8)
|
||||
#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI (2 << 8)
|
||||
#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI (3 << 8)
|
||||
#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
|
||||
#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
|
||||
#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
|
||||
#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
|
||||
#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
|
||||
#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
|
||||
#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED (0 << 6)
|
||||
#define GHWCFG2_HS_PHY_TYPE_UTMI (1 << 6)
|
||||
#define GHWCFG2_HS_PHY_TYPE_ULPI (2 << 6)
|
||||
#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI (3 << 6)
|
||||
#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
|
||||
#define GHWCFG2_HS_PHY_TYPE_UTMI 1
|
||||
#define GHWCFG2_HS_PHY_TYPE_ULPI 2
|
||||
#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
|
||||
#define GHWCFG2_POINT2POINT (1 << 5)
|
||||
#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
|
||||
#define GHWCFG2_ARCHITECTURE_SHIFT 3
|
||||
#define GHWCFG2_SLAVE_ONLY_ARCH (0 << 3)
|
||||
#define GHWCFG2_EXT_DMA_ARCH (1 << 3)
|
||||
#define GHWCFG2_INT_DMA_ARCH (2 << 3)
|
||||
#define GHWCFG2_SLAVE_ONLY_ARCH 0
|
||||
#define GHWCFG2_EXT_DMA_ARCH 1
|
||||
#define GHWCFG2_INT_DMA_ARCH 2
|
||||
#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
|
||||
#define GHWCFG2_OP_MODE_SHIFT 0
|
||||
#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE (0 << 0)
|
||||
#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE (1 << 0)
|
||||
#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE (2 << 0)
|
||||
#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE (3 << 0)
|
||||
#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE (4 << 0)
|
||||
#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST (5 << 0)
|
||||
#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST (6 << 0)
|
||||
#define GHWCFG2_OP_MODE_UNDEFINED (7 << 0)
|
||||
#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
|
||||
#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
|
||||
#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
|
||||
#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
|
||||
#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
|
||||
#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
|
||||
#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
|
||||
#define GHWCFG2_OP_MODE_UNDEFINED 7
|
||||
|
||||
#define GHWCFG3 HSOTG_REG(0x004c)
|
||||
#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
|
||||
|
|
@ -417,10 +417,10 @@
|
|||
#define DCFG_NZ_STS_OUT_HSHK (1 << 2)
|
||||
#define DCFG_DEVSPD_MASK (0x3 << 0)
|
||||
#define DCFG_DEVSPD_SHIFT 0
|
||||
#define DCFG_DEVSPD_HS (0 << 0)
|
||||
#define DCFG_DEVSPD_FS (1 << 0)
|
||||
#define DCFG_DEVSPD_LS (2 << 0)
|
||||
#define DCFG_DEVSPD_FS48 (3 << 0)
|
||||
#define DCFG_DEVSPD_HS 0
|
||||
#define DCFG_DEVSPD_FS 1
|
||||
#define DCFG_DEVSPD_LS 2
|
||||
#define DCFG_DEVSPD_FS48 3
|
||||
|
||||
#define DCTL HSOTG_REG(0x804)
|
||||
#define DCTL_PWRONPRGDONE (1 << 11)
|
||||
|
|
@ -443,10 +443,10 @@
|
|||
#define DSTS_ERRATICERR (1 << 3)
|
||||
#define DSTS_ENUMSPD_MASK (0x3 << 1)
|
||||
#define DSTS_ENUMSPD_SHIFT 1
|
||||
#define DSTS_ENUMSPD_HS (0 << 1)
|
||||
#define DSTS_ENUMSPD_FS (1 << 1)
|
||||
#define DSTS_ENUMSPD_LS (2 << 1)
|
||||
#define DSTS_ENUMSPD_FS48 (3 << 1)
|
||||
#define DSTS_ENUMSPD_HS 0
|
||||
#define DSTS_ENUMSPD_FS 1
|
||||
#define DSTS_ENUMSPD_LS 2
|
||||
#define DSTS_ENUMSPD_FS48 3
|
||||
#define DSTS_SUSPSTS (1 << 0)
|
||||
|
||||
#define DIEPMSK HSOTG_REG(0x810)
|
||||
|
|
@ -494,10 +494,10 @@
|
|||
*/
|
||||
#define D0EPCTL_MPS_MASK (0x3 << 0)
|
||||
#define D0EPCTL_MPS_SHIFT 0
|
||||
#define D0EPCTL_MPS_64 (0 << 0)
|
||||
#define D0EPCTL_MPS_32 (1 << 0)
|
||||
#define D0EPCTL_MPS_16 (2 << 0)
|
||||
#define D0EPCTL_MPS_8 (3 << 0)
|
||||
#define D0EPCTL_MPS_64 0
|
||||
#define D0EPCTL_MPS_32 1
|
||||
#define D0EPCTL_MPS_16 2
|
||||
#define D0EPCTL_MPS_8 3
|
||||
|
||||
#define DXEPCTL_EPENA (1 << 31)
|
||||
#define DXEPCTL_EPDIS (1 << 30)
|
||||
|
|
@ -515,10 +515,10 @@
|
|||
#define DXEPCTL_SNP (1 << 20)
|
||||
#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
|
||||
#define DXEPCTL_EPTYPE_SHIFT 18
|
||||
#define DXEPCTL_EPTYPE_CONTROL (0 << 18)
|
||||
#define DXEPCTL_EPTYPE_ISO (1 << 18)
|
||||
#define DXEPCTL_EPTYPE_BULK (2 << 18)
|
||||
#define DXEPCTL_EPTYPE_INTTERUPT (3 << 18)
|
||||
#define DXEPCTL_EPTYPE_CONTROL 0
|
||||
#define DXEPCTL_EPTYPE_ISO 1
|
||||
#define DXEPCTL_EPTYPE_BULK 2
|
||||
#define DXEPCTL_EPTYPE_INTTERUPT 3
|
||||
#define DXEPCTL_NAKSTS (1 << 17)
|
||||
#define DXEPCTL_DPID (1 << 16)
|
||||
#define DXEPCTL_EOFRNUM (1 << 16)
|
||||
|
|
@ -638,9 +638,9 @@
|
|||
#define HCFG_FSLSSUPP (1 << 2)
|
||||
#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
|
||||
#define HCFG_FSLSPCLKSEL_SHIFT 0
|
||||
#define HCFG_FSLSPCLKSEL_30_60_MHZ (0 << 0)
|
||||
#define HCFG_FSLSPCLKSEL_48_MHZ (1 << 0)
|
||||
#define HCFG_FSLSPCLKSEL_6_MHZ (2 << 0)
|
||||
#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
|
||||
#define HCFG_FSLSPCLKSEL_48_MHZ 1
|
||||
#define HCFG_FSLSPCLKSEL_6_MHZ 2
|
||||
|
||||
#define HFIR HSOTG_REG(0x0404)
|
||||
#define HFIR_FRINT_MASK (0xffff << 0)
|
||||
|
|
@ -673,9 +673,9 @@
|
|||
#define HPRT0 HSOTG_REG(0x0440)
|
||||
#define HPRT0_SPD_MASK (0x3 << 17)
|
||||
#define HPRT0_SPD_SHIFT 17
|
||||
#define HPRT0_SPD_HIGH_SPEED (0 << 17)
|
||||
#define HPRT0_SPD_FULL_SPEED (1 << 17)
|
||||
#define HPRT0_SPD_LOW_SPEED (2 << 17)
|
||||
#define HPRT0_SPD_HIGH_SPEED 0
|
||||
#define HPRT0_SPD_FULL_SPEED 1
|
||||
#define HPRT0_SPD_LOW_SPEED 2
|
||||
#define HPRT0_TSTCTL_MASK (0xf << 13)
|
||||
#define HPRT0_TSTCTL_SHIFT 13
|
||||
#define HPRT0_PWR (1 << 12)
|
||||
|
|
@ -713,10 +713,10 @@
|
|||
#define HCSPLT_COMPSPLT (1 << 16)
|
||||
#define HCSPLT_XACTPOS_MASK (0x3 << 14)
|
||||
#define HCSPLT_XACTPOS_SHIFT 14
|
||||
#define HCSPLT_XACTPOS_MID (0 << 14)
|
||||
#define HCSPLT_XACTPOS_END (1 << 14)
|
||||
#define HCSPLT_XACTPOS_BEGIN (2 << 14)
|
||||
#define HCSPLT_XACTPOS_ALL (3 << 14)
|
||||
#define HCSPLT_XACTPOS_MID 0
|
||||
#define HCSPLT_XACTPOS_END 1
|
||||
#define HCSPLT_XACTPOS_BEGIN 2
|
||||
#define HCSPLT_XACTPOS_ALL 3
|
||||
#define HCSPLT_HUBADDR_MASK (0x7f << 7)
|
||||
#define HCSPLT_HUBADDR_SHIFT 7
|
||||
#define HCSPLT_PRTADDR_MASK (0x7f << 0)
|
||||
|
|
@ -744,11 +744,11 @@
|
|||
#define TSIZ_DOPNG (1 << 31)
|
||||
#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
|
||||
#define TSIZ_SC_MC_PID_SHIFT 29
|
||||
#define TSIZ_SC_MC_PID_DATA0 (0 << 29)
|
||||
#define TSIZ_SC_MC_PID_DATA2 (1 << 29)
|
||||
#define TSIZ_SC_MC_PID_DATA1 (2 << 29)
|
||||
#define TSIZ_SC_MC_PID_MDATA (3 << 29)
|
||||
#define TSIZ_SC_MC_PID_SETUP (3 << 29)
|
||||
#define TSIZ_SC_MC_PID_DATA0 0
|
||||
#define TSIZ_SC_MC_PID_DATA2 1
|
||||
#define TSIZ_SC_MC_PID_DATA1 2
|
||||
#define TSIZ_SC_MC_PID_MDATA 3
|
||||
#define TSIZ_SC_MC_PID_SETUP 3
|
||||
#define TSIZ_PKTCNT_MASK (0x3ff << 19)
|
||||
#define TSIZ_PKTCNT_SHIFT 19
|
||||
#define TSIZ_NTD_MASK (0xff << 8)
|
||||
|
|
|
|||
Loading…
Reference in New Issue