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Merge branch 'linus' into core/urgent 

Update with Linus tree so fixes for the same can be applied.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
hifive-unleashed-5.1
Thomas Gleixner 2013-05-05 08:24:42 +02:00
parent fd29f424d4 ce857229e0
commit f99e44a7f3
7459 changed files with 405917 additions and 251939 deletions
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4
CREDITS
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@ -761,6 +761,10 @@ S: Northampton
S: NN1 3QT
S: United Kingdom
N: Massimo Dal Zotto
E: dz@debian.org
D: i8k Dell laptop SMM driver
N: Uwe Dannowski
E: Uwe.Dannowski@ira.uka.de
W: http://i30www.ira.uka.de/~dannowsk/

7
Documentation/ABI/testing/sysfs-bus-mei 100644
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@ -0,0 +1,7 @@
What: /sys/bus/mei/devices/.../modalias
Date: March 2013
KernelVersion: 3.10
Contact: Samuel Ortiz <sameo@linux.intel.com>
linux-mei@linux.intel.com
Description: Stores the same MODALIAS value emitted by uevent
Format: mei:<mei device name>

6
Documentation/ABI/testing/sysfs-bus-usb
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@ -32,7 +32,7 @@ Date: January 2008
KernelVersion: 2.6.25
Contact: Sarah Sharp <sarah.a.sharp@intel.com>
Description:
If CONFIG_PM and CONFIG_USB_SUSPEND are enabled, then this file
If CONFIG_PM_RUNTIME is enabled then this file
is present. When read, it returns the total time (in msec)
that the USB device has been connected to the machine. This
file is read-only.
@ -45,7 +45,7 @@ Date: January 2008
KernelVersion: 2.6.25
Contact: Sarah Sharp <sarah.a.sharp@intel.com>
Description:
If CONFIG_PM and CONFIG_USB_SUSPEND are enabled, then this file
If CONFIG_PM_RUNTIME is enabled then this file
is present. When read, it returns the total time (in msec)
that the USB device has been active, i.e. not in a suspended
state. This file is read-only.
@ -187,7 +187,7 @@ What: /sys/bus/usb/devices/.../power/usb2_hardware_lpm
Date: September 2011
Contact: Andiry Xu <andiry.xu@amd.com>
Description:
If CONFIG_USB_SUSPEND is set and a USB 2.0 lpm-capable device
If CONFIG_PM_RUNTIME is set and a USB 2.0 lpm-capable device
is plugged in to a xHCI host which support link PM, it will
perform a LPM test; if the test is passed and host supports
USB2 hardware LPM (xHCI 1.0 feature), USB2 hardware LPM will

8
Documentation/ABI/testing/sysfs-class-net-mesh
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@ -67,6 +67,14 @@ Description:
Defines the penalty which will be applied to an
originator message's tq-field on every hop.
What: /sys/class/net/<mesh_iface>/mesh/network_coding
Date: Nov 2012
Contact: Martin Hundeboll <martin@hundeboll.net>
Description:
Controls whether Network Coding (using some magic
to send fewer wifi packets but still the same
content) is enabled or not.
What: /sys/class/net/<mesh_iface>/mesh/orig_interval
Date: May 2010
Contact: Marek Lindner <lindner_marek@yahoo.de>

44
Documentation/ABI/testing/sysfs-devices-lpss_ltr 100644
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@ -0,0 +1,44 @@
What: /sys/devices/.../lpss_ltr/
Date: March 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
The /sys/devices/.../lpss_ltr/ directory is only present for
devices included into the Intel Lynxpoint Low Power Subsystem
(LPSS). If present, it contains attributes containing the LTR
mode and the values of LTR registers of the device.
What: /sys/devices/.../lpss_ltr/ltr_mode
Date: March 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
The /sys/devices/.../lpss_ltr/ltr_mode attribute contains an
integer number (0 or 1) indicating whether or not the devices'
LTR functionality is working in the software mode (1).
This attribute is read-only. If the device's runtime PM status
is not "active", attempts to read from this attribute cause
-EAGAIN to be returned.
What: /sys/devices/.../lpss_ltr/auto_ltr
Date: March 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
The /sys/devices/.../lpss_ltr/auto_ltr attribute contains the
current value of the device's AUTO_LTR register (raw)
represented as an 8-digit hexadecimal number.
This attribute is read-only. If the device's runtime PM status
is not "active", attempts to read from this attribute cause
-EAGAIN to be returned.
What: /sys/devices/.../lpss_ltr/sw_ltr
Date: March 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
The /sys/devices/.../lpss_ltr/auto_ltr attribute contains the
current value of the device's SW_LTR register (raw) represented
as an 8-digit hexadecimal number.
This attribute is read-only. If the device's runtime PM status
is not "active", attempts to read from this attribute cause
-EAGAIN to be returned.

13
Documentation/ABI/testing/sysfs-devices-power_resources_wakeup 100644
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@ -0,0 +1,13 @@
What: /sys/devices/.../power_resources_wakeup/
Date: April 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
The /sys/devices/.../power_resources_wakeup/ directory is only
present for device objects representing ACPI device nodes that
require ACPI power resources for wakeup signaling.
If present, it contains symbolic links to device directories
representing ACPI power resources that need to be turned on for
the given device node to be able to signal wakeup. The names of
the links are the same as the names of the directories they
point to.

12
Documentation/ABI/testing/sysfs-devices-system-cpu
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@ -173,3 +173,15 @@ Description: Processor frequency boosting control
Boosting allows the CPU and the firmware to run at a frequency
beyound it's nominal limit.
More details can be found in Documentation/cpu-freq/boost.txt
What: /sys/devices/system/cpu/cpu#/crash_notes
/sys/devices/system/cpu/cpu#/crash_notes_size
Date: April 2013
Contact: kexec@lists.infradead.org
Description: address and size of the percpu note.
crash_notes: the physical address of the memory that holds the
note of cpu#.
crash_notes_size: size of the note of cpu#.

12
Documentation/ABI/testing/sysfs-driver-hid-roccat-isku
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@ -101,7 +101,8 @@ Date: June 2011
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When written, this file lets one set the backlight intensity for
a specific profile. Profile number is included in written data.
The data has to be 10 bytes long.
The data has to be 10 bytes long for Isku, IskuFX needs 16 bytes
of data.
Before reading this file, control has to be written to select
which profile to read.
Users: http://roccat.sourceforge.net
@ -141,3 +142,12 @@ Description: When written, this file lets one trigger easyshift functionality
The data has to be 16 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/talkfx
Date: February 2013
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When written, this file lets one trigger temporary color schemes
from the host.
The data has to be 16 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net

105
Documentation/ABI/testing/sysfs-driver-hid-roccat-konepure 100644
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@ -0,0 +1,105 @@
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/actual_profile
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: The mouse can store 5 profiles which can be switched by the
press of a button. actual_profile holds number of actual profile.
This value is persistent, so its value determines the profile
that's active when the mouse is powered on next time.
When written, the mouse activates the set profile immediately.
The data has to be 3 bytes long.
The mouse will reject invalid data.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/control
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When written, this file lets one select which data from which
profile will be read next. The data has to be 3 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/info
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When read, this file returns general data like firmware version.
When written, the device can be reset.
The data is 6 bytes long.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/macro
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: The mouse can store a macro with max 500 key/button strokes
internally.
When written, this file lets one set the sequence for a specific
button for a specific profile. Button and profile numbers are
included in written data. The data has to be 2082 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/profile_buttons
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: The mouse can store 5 profiles which can be switched by the
press of a button. A profile is split in settings and buttons.
profile_buttons holds information about button layout.
When written, this file lets one write the respective profile
buttons back to the mouse. The data has to be 59 bytes long.
The mouse will reject invalid data.
Which profile to write is determined by the profile number
contained in the data.
Before reading this file, control has to be written to select
which profile to read.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/profile_settings
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: The mouse can store 5 profiles which can be switched by the
press of a button. A profile is split in settings and buttons.
profile_settings holds information like resolution, sensitivity
and light effects.
When written, this file lets one write the respective profile
settings back to the mouse. The data has to be 31 bytes long.
The mouse will reject invalid data.
Which profile to write is determined by the profile number
contained in the data.
Before reading this file, control has to be written to select
which profile to read.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/sensor
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: The mouse has a tracking- and a distance-control-unit. These
can be activated/deactivated and the lift-off distance can be
set. The data has to be 6 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/talk
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: Used to active some easy* functions of the mouse from outside.
The data has to be 16 bytes long.
This file is writeonly.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/tcu
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When written a calibration process for the tracking control unit
can be initiated/cancelled. Also lets one read/write sensor
registers.
The data has to be 4 bytes long.
Users: http://roccat.sourceforge.net
What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/konepure/roccatkonepure<minor>/tcu_image
Date: December 2012
Contact: Stefan Achatz <erazor_de@users.sourceforge.net>
Description: When read the mouse returns a 30x30 pixel image of the
sampled underground. This works only in the course of a
calibration process initiated with tcu.
The returned data is 1028 bytes in size.
This file is readonly.
Users: http://roccat.sourceforge.net

26
Documentation/ABI/testing/sysfs-firmware-acpi
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@ -18,6 +18,32 @@ Description:
yoffset: The number of pixels between the top of the screen
and the top edge of the image.
What: /sys/firmware/acpi/hotplug/
Date: February 2013
Contact: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Description:
There are separate hotplug profiles for different classes of
devices supported by ACPI, such as containers, memory modules,
processors, PCI root bridges etc. A hotplug profile for a given
class of devices is a collection of settings defining the way
that class of devices will be handled by the ACPI core hotplug
code. Those profiles are represented in sysfs as subdirectories
of /sys/firmware/acpi/hotplug/.
The following setting is available to user space for each
hotplug profile:
enabled: If set, the ACPI core will handle notifications of
hotplug events associated with the given class of
devices and will allow those devices to be ejected with
the help of the _EJ0 control method. Unsetting it
effectively disables hotplug for the correspoinding
class of devices.
The value of the above attribute is an integer number: 1 (set)
or 0 (unset). Attempts to write any other values to it will
cause -EINVAL to be returned.
What: /sys/firmware/acpi/interrupts/
Date: February 2008
Contact: Len Brown <lenb@kernel.org>

2
Documentation/DocBook/80211.tmpl
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@ -437,7 +437,7 @@
</section>
!Finclude/net/mac80211.h ieee80211_get_buffered_bc
!Finclude/net/mac80211.h ieee80211_beacon_get
!Finclude/net/mac80211.h ieee80211_sta_eosp_irqsafe
!Finclude/net/mac80211.h ieee80211_sta_eosp
!Finclude/net/mac80211.h ieee80211_frame_release_type
!Finclude/net/mac80211.h ieee80211_sta_ps_transition
!Finclude/net/mac80211.h ieee80211_sta_ps_transition_ni

52
Documentation/DocBook/media/dvb/dvbproperty.xml
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@ -1,6 +1,6 @@
<section id="FE_GET_SET_PROPERTY">
<title><constant>FE_GET_PROPERTY/FE_SET_PROPERTY</constant></title>
<para>This section describes the DVB version 5 extention of the DVB-API, also
<para>This section describes the DVB version 5 extension of the DVB-API, also
called "S2API", as this API were added to provide support for DVB-S2. It was
designed to be able to replace the old frontend API. Yet, the DISEQC and
the capability ioctls weren't implemented yet via the new way.</para>
@ -903,14 +903,12 @@ enum fe_interleaving {
<constant>svalue</constant> is for signed values of the measure (dB measures)
and <constant>uvalue</constant> is for unsigned values (counters, relative scale)</para></listitem>
<listitem><para><constant>scale</constant> - Scale for the value. It can be:</para>
<section id = "fecap-scale-params">
<itemizedlist mark='bullet'>
<itemizedlist mark='bullet' id="fecap-scale-params">
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - The parameter is supported by the frontend, but it was not possible to collect it (could be a transitory or permanent condition)</para></listitem>
<listitem><para><constant>FE_SCALE_DECIBEL</constant> - parameter is a signed value, measured in 1/1000 dB</para></listitem>
<listitem><para><constant>FE_SCALE_RELATIVE</constant> - parameter is a unsigned value, where 0 means 0% and 65535 means 100%.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - parameter is a unsigned value that counts the occurrence of an event, like bit error, block error, or lapsed time.</para></listitem>
</itemizedlist>
</section>
</listitem>
</itemizedlist>
<section id="DTV-STAT-SIGNAL-STRENGTH">
@ -918,9 +916,9 @@ enum fe_interleaving {
<para>Indicates the signal strength level at the analog part of the tuner or of the demod.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_DECIBEL</constant> - signal strength is in 0.0001 dBm units, power measured in miliwatts. This value is generally negative.</listitem>
<listitem><constant>FE_SCALE_RELATIVE</constant> - The frontend provides a 0% to 100% measurement for power (actually, 0 to 65535).</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_DECIBEL</constant> - signal strength is in 0.0001 dBm units, power measured in miliwatts. This value is generally negative.</para></listitem>
<listitem><para><constant>FE_SCALE_RELATIVE</constant> - The frontend provides a 0% to 100% measurement for power (actually, 0 to 65535).</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-CNR">
@ -928,9 +926,9 @@ enum fe_interleaving {
<para>Indicates the Signal to Noise ratio for the main carrier.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_DECIBEL</constant> - Signal/Noise ratio is in 0.0001 dB units.</listitem>
<listitem><constant>FE_SCALE_RELATIVE</constant> - The frontend provides a 0% to 100% measurement for Signal/Noise (actually, 0 to 65535).</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_DECIBEL</constant> - Signal/Noise ratio is in 0.0001 dB units.</para></listitem>
<listitem><para><constant>FE_SCALE_RELATIVE</constant> - The frontend provides a 0% to 100% measurement for Signal/Noise (actually, 0 to 65535).</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-PRE-ERROR-BIT-COUNT">
@ -943,8 +941,8 @@ enum fe_interleaving {
The frontend may reset it when a channel/transponder is tuned.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of error bits counted before the inner coding.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of error bits counted before the inner coding.</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-PRE-TOTAL-BIT-COUNT">
@ -952,14 +950,14 @@ enum fe_interleaving {
<para>Measures the amount of bits received before the inner code block, during the same period as
<link linkend="DTV-STAT-PRE-ERROR-BIT-COUNT"><constant>DTV_STAT_PRE_ERROR_BIT_COUNT</constant></link> measurement was taken.</para>
<para>It should be noticed that this measurement can be smaller than the total amount of bits on the transport stream,
as the frontend may need to manually restart the measurement, loosing some data between each measurement interval.</para>
as the frontend may need to manually restart the measurement, losing some data between each measurement interval.</para>
<para>This measurement is monotonically increased, as the frontend gets more bit count measurements.
The frontend may reset it when a channel/transponder is tuned.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of bits counted while measuring
<link linkend="DTV-STAT-PRE-ERROR-BIT-COUNT"><constant>DTV_STAT_PRE_ERROR_BIT_COUNT</constant></link>.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of bits counted while measuring
<link linkend="DTV-STAT-PRE-ERROR-BIT-COUNT"><constant>DTV_STAT_PRE_ERROR_BIT_COUNT</constant></link>.</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-POST-ERROR-BIT-COUNT">
@ -972,8 +970,8 @@ enum fe_interleaving {
The frontend may reset it when a channel/transponder is tuned.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of error bits counted after the inner coding.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of error bits counted after the inner coding.</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-POST-TOTAL-BIT-COUNT">
@ -981,14 +979,14 @@ enum fe_interleaving {
<para>Measures the amount of bits received after the inner coding, during the same period as
<link linkend="DTV-STAT-POST-ERROR-BIT-COUNT"><constant>DTV_STAT_POST_ERROR_BIT_COUNT</constant></link> measurement was taken.</para>
<para>It should be noticed that this measurement can be smaller than the total amount of bits on the transport stream,
as the frontend may need to manually restart the measurement, loosing some data between each measurement interval.</para>
as the frontend may need to manually restart the measurement, losing some data between each measurement interval.</para>
<para>This measurement is monotonically increased, as the frontend gets more bit count measurements.
The frontend may reset it when a channel/transponder is tuned.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of bits counted while measuring
<link linkend="DTV-STAT-POST-ERROR-BIT-COUNT"><constant>DTV_STAT_POST_ERROR_BIT_COUNT</constant></link>.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of bits counted while measuring
<link linkend="DTV-STAT-POST-ERROR-BIT-COUNT"><constant>DTV_STAT_POST_ERROR_BIT_COUNT</constant></link>.</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-ERROR-BLOCK-COUNT">
@ -998,8 +996,8 @@ enum fe_interleaving {
The frontend may reset it when a channel/transponder is tuned.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of error blocks counted after the outer coding.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of error blocks counted after the outer coding.</para></listitem>
</itemizedlist>
</section>
<section id="DTV-STAT-TOTAL-BLOCK-COUNT">
@ -1011,9 +1009,9 @@ enum fe_interleaving {
by <link linkend="DTV-STAT-TOTAL-BLOCK-COUNT"><constant>DTV-STAT-TOTAL-BLOCK-COUNT</constant></link>.</para>
<para>Possible scales for this metric are:</para>
<itemizedlist mark='bullet'>
<listitem><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</listitem>
<listitem><constant>FE_SCALE_COUNTER</constant> - Number of blocks counted while measuring
<link linkend="DTV-STAT-ERROR-BLOCK-COUNT"><constant>DTV_STAT_ERROR_BLOCK_COUNT</constant></link>.</listitem>
<listitem><para><constant>FE_SCALE_NOT_AVAILABLE</constant> - it failed to measure it, or the measurement was not complete yet.</para></listitem>
<listitem><para><constant>FE_SCALE_COUNTER</constant> - Number of blocks counted while measuring
<link linkend="DTV-STAT-ERROR-BLOCK-COUNT"><constant>DTV_STAT_ERROR_BLOCK_COUNT</constant></link>.</para></listitem>
</itemizedlist>
</section>
</section>

14
Documentation/DocBook/media/v4l/common.xml
View File

@ -749,15 +749,6 @@ polarities, frontporch, backporch etc. The <filename>linux/v4l2-dv-timings.h</fi
header can be used to get the timings of the formats in the <xref linkend="cea861" /> and
<xref linkend="vesadmt" /> standards.
</para>
</listitem>
<listitem>
<para>DV Presets: Digital Video (DV) presets (<emphasis role="bold">deprecated</emphasis>).
These are IDs representing a
video timing at the input/output. Presets are pre-defined timings implemented
by the hardware according to video standards. A __u32 data type is used to represent
a preset unlike the bit mask that is used in &v4l2-std-id; allowing future extensions
to support as many different presets as needed. This API is deprecated in favor of the DV Timings
API.</para>
</listitem>
</itemizedlist>
<para>To enumerate and query the attributes of the DV timings supported by a device,
@ -766,11 +757,6 @@ API.</para>
&VIDIOC-S-DV-TIMINGS; ioctl and to get current DV timings they use the
&VIDIOC-G-DV-TIMINGS; ioctl. To detect the DV timings as seen by the video receiver applications
use the &VIDIOC-QUERY-DV-TIMINGS; ioctl.</para>
<para>To enumerate and query the attributes of DV presets supported by a device,
applications use the &VIDIOC-ENUM-DV-PRESETS; ioctl. To get the current DV preset,
applications use the &VIDIOC-G-DV-PRESET; ioctl and to set a preset they use the
&VIDIOC-S-DV-PRESET; ioctl. To detect the preset as seen by the video receiver applications
use the &VIDIOC-QUERY-DV-PRESET; ioctl.</para>
<para>Applications can make use of the <xref linkend="input-capabilities" /> and
<xref linkend="output-capabilities"/> flags to decide what ioctls are available to set the
video timings for the device.</para>

24
Documentation/DocBook/media/v4l/compat.xml
View File

@ -2310,6 +2310,9 @@ more information.</para>
<listitem>
<para>Added FM Modulator (FM TX) Extended Control Class: <constant>V4L2_CTRL_CLASS_FM_TX</constant> and their Control IDs.</para>
</listitem>
<listitem>
<para>Added FM Receiver (FM RX) Extended Control Class: <constant>V4L2_CTRL_CLASS_FM_RX</constant> and their Control IDs.</para>
</listitem>
<listitem>
<para>Added Remote Controller chapter, describing the default Remote Controller mapping for media devices.</para>
</listitem>
@ -2493,6 +2496,23 @@ that used it. It was originally scheduled for removal in 2.6.35.
</orderedlist>
</section>
<section>
<title>V4L2 in Linux 3.10</title>
<orderedlist>
<listitem>
<para>Removed obsolete and unused DV_PRESET ioctls
VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET, VIDIOC_QUERY_DV_PRESET and
VIDIOC_ENUM_DV_PRESET. Remove the related v4l2_input/output capability
flags V4L2_IN_CAP_PRESETS and V4L2_OUT_CAP_PRESETS.
</para>
</listitem>
<listitem>
<para>Added new debugging ioctl &VIDIOC-DBG-G-CHIP-INFO;.
</para>
</listitem>
</orderedlist>
</section>
<section id="other">
<title>Relation of V4L2 to other Linux multimedia APIs</title>
@ -2625,8 +2645,8 @@ interfaces and should not be implemented in new drivers.</para>
<xref linkend="extended-controls" />.</para>
</listitem>
<listitem>
<para>&VIDIOC-G-DV-PRESET;, &VIDIOC-S-DV-PRESET;, &VIDIOC-ENUM-DV-PRESETS; and
&VIDIOC-QUERY-DV-PRESET; ioctls. Use the DV Timings API (<xref linkend="dv-timings" />).</para>
<para>VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET, VIDIOC_ENUM_DV_PRESETS and
VIDIOC_QUERY_DV_PRESET ioctls. Use the DV Timings API (<xref linkend="dv-timings" />).</para>
</listitem>
<listitem>
<para><constant>VIDIOC_SUBDEV_G_CROP</constant> and

87
Documentation/DocBook/media/v4l/controls.xml
View File

@ -2299,6 +2299,12 @@ Possible values are:</entry>
</entrytbl>
</row>
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER</constant>&nbsp;</entry>
<entry>boolean</entry>
</row><row><entry spanname="descr">Repeat the video sequence headers. Repeating these
headers makes random access to the video stream easier. Applicable to the MPEG1, 2 and 4 encoder.</entry>
</row>
<row>
<entry spanname="id"><constant>V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER</constant>&nbsp;</entry>
<entry>boolean</entry>
@ -3136,6 +3142,13 @@ giving priority to the center of the metered area.</entry>
<entry><constant>V4L2_EXPOSURE_METERING_SPOT</constant>&nbsp;</entry>
<entry>Measure only very small area at the center of the frame.</entry>
</row>
<row>
<entry><constant>V4L2_EXPOSURE_METERING_MATRIX</constant>&nbsp;</entry>
<entry>A multi-zone metering. The light intensity is measured
in several points of the frame and the the results are combined. The
algorithm of the zones selection and their significance in calculating the
final value is device dependant.</entry>
</row>
</tbody>
</entrytbl>
</row>
@ -3848,7 +3861,7 @@ in Hz. The range and step are driver-specific.</entry>
</row>
<row>
<entry spanname="id"><constant>V4L2_CID_TUNE_PREEMPHASIS</constant>&nbsp;</entry>
<entry>integer</entry>
<entry>enum v4l2_preemphasis</entry>
</row>
<row id="v4l2-preemphasis"><entry spanname="descr">Configures the pre-emphasis value for broadcasting.
A pre-emphasis filter is applied to the broadcast to accentuate the high audio frequencies.
@ -4687,4 +4700,76 @@ interface and may change in the future.</para>
</table>
</section>
<section id="fm-rx-controls">
<title>FM Receiver Control Reference</title>
<para>The FM Receiver (FM_RX) class includes controls for common features of
FM Reception capable devices.</para>
<table pgwide="1" frame="none" id="fm-rx-control-id">
<title>FM_RX Control IDs</title>
<tgroup cols="4">
<colspec colname="c1" colwidth="1*" />
<colspec colname="c2" colwidth="6*" />
<colspec colname="c3" colwidth="2*" />
<colspec colname="c4" colwidth="6*" />
<spanspec namest="c1" nameend="c2" spanname="id" />
<spanspec namest="c2" nameend="c4" spanname="descr" />
<thead>
<row>
<entry spanname="id" align="left">ID</entry>
<entry align="left">Type</entry>
</row><row rowsep="1"><entry spanname="descr" align="left">Description</entry>
</row>
</thead>
<tbody valign="top">
<row><entry></entry></row>
<row>
<entry spanname="id"><constant>V4L2_CID_FM_RX_CLASS</constant>&nbsp;</entry>
<entry>class</entry>
</row><row><entry spanname="descr">The FM_RX class
descriptor. Calling &VIDIOC-QUERYCTRL; for this control will return a
description of this control class.</entry>
</row>
<row>
<entry spanname="id"><constant>V4L2_CID_RDS_RECEPTION</constant>&nbsp;</entry>
<entry>boolean</entry>
</row><row><entry spanname="descr">Enables/disables RDS
reception by the radio tuner</entry>
</row>
<row>
<entry spanname="id"><constant>V4L2_CID_TUNE_DEEMPHASIS</constant>&nbsp;</entry>
<entry>enum v4l2_deemphasis</entry>
</row>
<row id="v4l2-deemphasis"><entry spanname="descr">Configures the de-emphasis value for reception.
A de-emphasis filter is applied to the broadcast to accentuate the high audio frequencies.
Depending on the region, a time constant of either 50 or 75 useconds is used. The enum&nbsp;v4l2_deemphasis
defines possible values for de-emphasis. Here they are:</entry>
</row><row>
<entrytbl spanname="descr" cols="2">
<tbody valign="top">
<row>
<entry><constant>V4L2_DEEMPHASIS_DISABLED</constant>&nbsp;</entry>
<entry>No de-emphasis is applied.</entry>
</row>
<row>
<entry><constant>V4L2_DEEMPHASIS_50_uS</constant>&nbsp;</entry>
<entry>A de-emphasis of 50 uS is used.</entry>
</row>
<row>
<entry><constant>V4L2_DEEMPHASIS_75_uS</constant>&nbsp;</entry>
<entry>A de-emphasis of 75 uS is used.</entry>
</row>
</tbody>
</entrytbl>
</row>
<row><entry></entry></row>
</tbody>
</tgroup>
</table>
</section>
</section>

6
Documentation/DocBook/media/v4l/io.xml
View File

@ -1145,6 +1145,12 @@ in which case caches have not been used.</entry>
same clock outside V4L2, use
<function>clock_gettime(2)</function> .</entry>
</row>
<row>
<entry><constant>V4L2_BUF_FLAG_TIMESTAMP_COPY</constant></entry>
<entry>0x4000</entry>
<entry>The CAPTURE buffer timestamp has been taken from the
corresponding OUTPUT buffer. This flag applies only to mem2mem devices.</entry>
</row>
</tbody>
</tgroup>
</table>

10
Documentation/DocBook/media/v4l/media-ioc-enum-entities.xml
View File

@ -272,6 +272,16 @@
<entry><constant>MEDIA_ENT_T_V4L2_SUBDEV_LENS</constant></entry>
<entry>Lens controller</entry>
</row>
<row>
<entry><constant>MEDIA_ENT_T_V4L2_SUBDEV_DECODER</constant></entry>
<entry>Video decoder, the basic function of the video decoder is to
accept analogue video from a wide variety of sources such as
broadcast, DVD players, cameras and video cassette recorders, in
either NTSC, PAL or HD format and still occasionally SECAM, separate
it into its component parts, luminance and chrominance, and output
it in some digital video standard, with appropriate embedded timing
signals.</entry>
</row>
</tbody>
</tgroup>
</table>

206
Documentation/DocBook/media/v4l/subdev-formats.xml
View File

@ -93,19 +93,35 @@
<table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-rgb">
<title>RGB formats</title>
<tgroup cols="11">
<tgroup cols="27">
<colspec colname="id" align="left" />
<colspec colname="code" align="center"/>
<colspec colname="bit" />
<colspec colnum="4" colname="b07" align="center" />
<colspec colnum="5" colname="b06" align="center" />
<colspec colnum="6" colname="b05" align="center" />
<colspec colnum="7" colname="b04" align="center" />
<colspec colnum="8" colname="b03" align="center" />
<colspec colnum="9" colname="b02" align="center" />
<colspec colnum="10" colname="b01" align="center" />
<colspec colnum="11" colname="b00" align="center" />
<spanspec namest="b07" nameend="b00" spanname="b0" />
<colspec colnum="4" colname="b23" align="center" />
<colspec colnum="5" colname="b22" align="center" />
<colspec colnum="6" colname="b21" align="center" />
<colspec colnum="7" colname="b20" align="center" />
<colspec colnum="8" colname="b19" align="center" />
<colspec colnum="9" colname="b18" align="center" />
<colspec colnum="10" colname="b17" align="center" />
<colspec colnum="11" colname="b16" align="center" />
<colspec colnum="12" colname="b15" align="center" />
<colspec colnum="13" colname="b14" align="center" />
<colspec colnum="14" colname="b13" align="center" />
<colspec colnum="15" colname="b12" align="center" />
<colspec colnum="16" colname="b11" align="center" />
<colspec colnum="17" colname="b10" align="center" />
<colspec colnum="18" colname="b09" align="center" />
<colspec colnum="19" colname="b08" align="center" />
<colspec colnum="20" colname="b07" align="center" />
<colspec colnum="21" colname="b06" align="center" />
<colspec colnum="22" colname="b05" align="center" />
<colspec colnum="23" colname="b04" align="center" />
<colspec colnum="24" colname="b03" align="center" />
<colspec colnum="25" colname="b02" align="center" />
<colspec colnum="26" colname="b01" align="center" />
<colspec colnum="27" colname="b00" align="center" />
<spanspec namest="b23" nameend="b00" spanname="b0" />
<thead>
<row>
<entry>Identifier</entry>
@ -117,6 +133,22 @@
<entry></entry>
<entry></entry>
<entry>Bit</entry>
<entry>23</entry>
<entry>22</entry>
<entry>21</entry>
<entry>20</entry>
<entry>19</entry>
<entry>18</entry>
<entry>17</entry>
<entry>16</entry>
<entry>15</entry>
<entry>14</entry>
<entry>13</entry>
<entry>12</entry>
<entry>11</entry>
<entry>10</entry>
<entry>9</entry>
<entry>8</entry>
<entry>7</entry>
<entry>6</entry>
<entry>5</entry>
@ -132,6 +164,7 @@
<entry>V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE</entry>
<entry>0x1001</entry>
<entry></entry>
&dash-ent-16;
<entry>0</entry>
<entry>0</entry>
<entry>0</entry>
@ -145,6 +178,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
@ -158,6 +192,7 @@
<entry>V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE</entry>
<entry>0x1002</entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
@ -171,6 +206,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>0</entry>
<entry>0</entry>
<entry>0</entry>
@ -184,6 +220,7 @@
<entry>V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE</entry>
<entry>0x1003</entry>
<entry></entry>
&dash-ent-16;
<entry>0</entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
@ -197,6 +234,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -210,6 +248,7 @@
<entry>V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE</entry>
<entry>0x1004</entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -223,6 +262,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>0</entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
@ -236,6 +276,7 @@
<entry>V4L2_MBUS_FMT_BGR565_2X8_BE</entry>
<entry>0x1005</entry>
<entry></entry>
&dash-ent-16;
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
@ -249,6 +290,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -262,6 +304,7 @@
<entry>V4L2_MBUS_FMT_BGR565_2X8_LE</entry>
<entry>0x1006</entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -275,6 +318,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
@ -288,6 +332,7 @@
<entry>V4L2_MBUS_FMT_RGB565_2X8_BE</entry>
<entry>0x1007</entry>
<entry></entry>
&dash-ent-16;
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
@ -301,6 +346,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -314,6 +360,7 @@
<entry>V4L2_MBUS_FMT_RGB565_2X8_LE</entry>
<entry>0x1008</entry>
<entry></entry>
&dash-ent-16;
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
@ -327,6 +374,7 @@
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-16;
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
@ -336,6 +384,144 @@
<entry>g<subscript>4</subscript></entry>
<entry>g<subscript>3</subscript></entry>
</row>
<row id="V4L2-MBUS-FMT-RGB666-1X18">
<entry>V4L2_MBUS_FMT_RGB666_1X18</entry>
<entry>0x1009</entry>
<entry></entry>
<entry>-</entry>
<entry>-</entry>
<entry>-</entry>
<entry>-</entry>
<entry>-</entry>
<entry>-</entry>
<entry>r<subscript>5</subscript></entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
<entry>r<subscript>1</subscript></entry>
<entry>r<subscript>0</subscript></entry>
<entry>g<subscript>5</subscript></entry>
<entry>g<subscript>4</subscript></entry>
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
<entry>b<subscript>5</subscript></entry>
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
<entry>b<subscript>1</subscript></entry>
<entry>b<subscript>0</subscript></entry>
</row>
<row id="V4L2-MBUS-FMT-RGB888-1X24">
<entry>V4L2_MBUS_FMT_RGB888_1X24</entry>
<entry>0x100a</entry>
<entry></entry>
<entry>r<subscript>7</subscript></entry>
<entry>r<subscript>6</subscript></entry>
<entry>r<subscript>5</subscript></entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
<entry>r<subscript>1</subscript></entry>
<entry>r<subscript>0</subscript></entry>
<entry>g<subscript>7</subscript></entry>
<entry>g<subscript>6</subscript></entry>
<entry>g<subscript>5</subscript></entry>
<entry>g<subscript>4</subscript></entry>
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
<entry>b<subscript>7</subscript></entry>
<entry>b<subscript>6</subscript></entry>
<entry>b<subscript>5</subscript></entry>
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
<entry>b<subscript>1</subscript></entry>
<entry>b<subscript>0</subscript></entry>
</row>
<row id="V4L2-MBUS-FMT-RGB888-2X12-BE">
<entry>V4L2_MBUS_FMT_RGB888_2X12_BE</entry>
<entry>0x100b</entry>
<entry></entry>
&dash-ent-10;
<entry>-</entry>
<entry>-</entry>
<entry>r<subscript>7</subscript></entry>
<entry>r<subscript>6</subscript></entry>
<entry>r<subscript>5</subscript></entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
<entry>r<subscript>1</subscript></entry>
<entry>r<subscript>0</subscript></entry>
<entry>g<subscript>7</subscript></entry>
<entry>g<subscript>6</subscript></entry>
<entry>g<subscript>5</subscript></entry>
<entry>g<subscript>4</subscript></entry>
</row>
<row>
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-10;
<entry>-</entry>
<entry>-</entry>
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
<entry>b<subscript>7</subscript></entry>
<entry>b<subscript>6</subscript></entry>
<entry>b<subscript>5</subscript></entry>
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
<entry>b<subscript>1</subscript></entry>
<entry>b<subscript>0</subscript></entry>
</row>
<row id="V4L2-MBUS-FMT-RGB888-2X12-LE">
<entry>V4L2_MBUS_FMT_RGB888_2X12_LE</entry>
<entry>0x100c</entry>
<entry></entry>
&dash-ent-10;
<entry>-</entry>
<entry>-</entry>
<entry>g<subscript>3</subscript></entry>
<entry>g<subscript>2</subscript></entry>
<entry>g<subscript>1</subscript></entry>
<entry>g<subscript>0</subscript></entry>
<entry>b<subscript>7</subscript></entry>
<entry>b<subscript>6</subscript></entry>
<entry>b<subscript>5</subscript></entry>
<entry>b<subscript>4</subscript></entry>
<entry>b<subscript>3</subscript></entry>
<entry>b<subscript>2</subscript></entry>
<entry>b<subscript>1</subscript></entry>
<entry>b<subscript>0</subscript></entry>
</row>
<row>
<entry></entry>
<entry></entry>
<entry></entry>
&dash-ent-10;
<entry>-</entry>
<entry>-</entry>
<entry>r<subscript>7</subscript></entry>
<entry>r<subscript>6</subscript></entry>
<entry>r<subscript>5</subscript></entry>
<entry>r<subscript>4</subscript></entry>
<entry>r<subscript>3</subscript></entry>
<entry>r<subscript>2</subscript></entry>
<entry>r<subscript>1</subscript></entry>
<entry>r<subscript>0</subscript></entry>
<entry>g<subscript>7</subscript></entry>
<entry>g<subscript>6</subscript></entry>
<entry>g<subscript>5</subscript></entry>
<entry>g<subscript>4</subscript></entry>
</row>
</tbody>
</tgroup>
</table>

19
Documentation/DocBook/media/v4l/v4l2.xml
View File

@ -124,6 +124,7 @@ Remote Controller chapter.</contrib>
<year>2010</year>
<year>2011</year>
<year>2012</year>
<year>2013</year>
<holder>Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin
Rubli, Andy Walls, Muralidharan Karicheri, Mauro Carvalho Chehab,
Pawel Osciak</holder>
@ -139,13 +140,23 @@ structs, ioctls) must be noted in more detail in the history chapter
(compat.xml), along with the possible impact on existing drivers and
applications. -->
<revision>
<revnumber>3.10</revnumber>
<date>2013-03-25</date>
<authorinitials>hv</authorinitials>
<revremark>Remove obsolete and unused DV_PRESET ioctls:
VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET, VIDIOC_QUERY_DV_PRESET and
VIDIOC_ENUM_DV_PRESET. Remove the related v4l2_input/output capability
flags V4L2_IN_CAP_PRESETS and V4L2_OUT_CAP_PRESETS. Added VIDIOC_DBG_G_CHIP_INFO.
</revremark>
</revision>
<revision>
<revnumber>3.9</revnumber>
<date>2012-12-03</date>
<authorinitials>sa, sn</authorinitials>
<revremark>Added timestamp types to v4l2_buffer.
Added <constant>V4L2_EVENT_CTRL_CH_RANGE</constant> control
event changes flag, see <xref linkend="changes-flags"/>.
Added V4L2_EVENT_CTRL_CH_RANGE control event changes flag.
</revremark>
</revision>
@ -537,6 +548,7 @@ and discussions on the V4L mailing list.</revremark>
&sub-create-bufs;
&sub-cropcap;
&sub-dbg-g-chip-ident;
&sub-dbg-g-chip-info;
&sub-dbg-g-register;
&sub-decoder-cmd;
&sub-dqevent;
@ -544,7 +556,6 @@ and discussions on the V4L mailing list.</revremark>
&sub-encoder-cmd;
&sub-enumaudio;
&sub-enumaudioout;
&sub-enum-dv-presets;
&sub-enum-dv-timings;
&sub-enum-fmt;
&sub-enum-framesizes;
@ -558,7 +569,6 @@ and discussions on the V4L mailing list.</revremark>
&sub-g-audioout;
&sub-g-crop;
&sub-g-ctrl;
&sub-g-dv-preset;
&sub-g-dv-timings;
&sub-g-enc-index;
&sub-g-ext-ctrls;
@ -582,7 +592,6 @@ and discussions on the V4L mailing list.</revremark>
&sub-querybuf;
&sub-querycap;
&sub-queryctrl;
&sub-query-dv-preset;
&sub-query-dv-timings;
&sub-querystd;
&sub-reqbufs;

9
Documentation/DocBook/media/v4l/vidioc-dbg-g-chip-ident.xml
View File

@ -200,10 +200,10 @@ the values from <xref linkend="chip-ids" />.</entry>
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_CHIP_MATCH_HOST</constant></entry>
<entry><constant>V4L2_CHIP_MATCH_BRIDGE</constant></entry>
<entry>0</entry>
<entry>Match the nth chip on the card, zero for the
host chip. Does not match &i2c; chips.</entry>
bridge chip. Does not match sub-devices.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_I2C_DRIVER</constant></entry>
@ -220,6 +220,11 @@ the values from <xref linkend="chip-ids" />.</entry>
<entry>3</entry>
<entry>Match the nth anciliary AC97 chip.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_SUBDEV</constant></entry>
<entry>4</entry>
<entry>Match the nth sub-device. Can't be used with this ioctl.</entry>
</row>
</tbody>
</tgroup>
</table>

223
Documentation/DocBook/media/v4l/vidioc-dbg-g-chip-info.xml 100644
View File

@ -0,0 +1,223 @@
<refentry id="vidioc-dbg-g-chip-info">
<refmeta>
<refentrytitle>ioctl VIDIOC_DBG_G_CHIP_INFO</refentrytitle>
&manvol;
</refmeta>
<refnamediv>
<refname>VIDIOC_DBG_G_CHIP_INFO</refname>
<refpurpose>Identify the chips on a TV card</refpurpose>
</refnamediv>
<refsynopsisdiv>
<funcsynopsis>
<funcprototype>
<funcdef>int <function>ioctl</function></funcdef>
<paramdef>int <parameter>fd</parameter></paramdef>
<paramdef>int <parameter>request</parameter></paramdef>
<paramdef>struct v4l2_dbg_chip_info
*<parameter>argp</parameter></paramdef>
</funcprototype>
</funcsynopsis>
</refsynopsisdiv>
<refsect1>
<title>Arguments</title>
<variablelist>
<varlistentry>
<term><parameter>fd</parameter></term>
<listitem>
<para>&fd;</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>request</parameter></term>
<listitem>
<para>VIDIOC_DBG_G_CHIP_INFO</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>argp</parameter></term>
<listitem>
<para></para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
<refsect1>
<title>Description</title>
<note>
<title>Experimental</title>
<para>This is an <link
linkend="experimental">experimental</link> interface and may change in
the future.</para>
</note>
<para>For driver debugging purposes this ioctl allows test
applications to query the driver about the chips present on the TV
card. Regular applications must not use it. When you found a chip
specific bug, please contact the linux-media mailing list (&v4l-ml;)
so it can be fixed.</para>
<para>Additionally the Linux kernel must be compiled with the
<constant>CONFIG_VIDEO_ADV_DEBUG</constant> option to enable this ioctl.</para>
<para>To query the driver applications must initialize the
<structfield>match.type</structfield> and
<structfield>match.addr</structfield> or <structfield>match.name</structfield>
fields of a &v4l2-dbg-chip-info;
and call <constant>VIDIOC_DBG_G_CHIP_INFO</constant> with a pointer to
this structure. On success the driver stores information about the
selected chip in the <structfield>name</structfield> and
<structfield>flags</structfield> fields. On failure the structure
remains unchanged.</para>
<para>When <structfield>match.type</structfield> is
<constant>V4L2_CHIP_MATCH_BRIDGE</constant>,
<structfield>match.addr</structfield> selects the nth bridge 'chip'
on the TV card. You can enumerate all chips by starting at zero and
incrementing <structfield>match.addr</structfield> by one until
<constant>VIDIOC_DBG_G_CHIP_INFO</constant> fails with an &EINVAL;.
The number zero always selects the bridge chip itself, &eg; the chip
connected to the PCI or USB bus. Non-zero numbers identify specific
parts of the bridge chip such as an AC97 register block.</para>
<para>When <structfield>match.type</structfield> is
<constant>V4L2_CHIP_MATCH_SUBDEV</constant>,
<structfield>match.addr</structfield> selects the nth sub-device. This
allows you to enumerate over all sub-devices.</para>
<para>On success, the <structfield>name</structfield> field will
contain a chip name and the <structfield>flags</structfield> field will
contain <constant>V4L2_CHIP_FL_READABLE</constant> if the driver supports
reading registers from the device or <constant>V4L2_CHIP_FL_WRITABLE</constant>
if the driver supports writing registers to the device.</para>
<para>We recommended the <application>v4l2-dbg</application>
utility over calling this ioctl directly. It is available from the
LinuxTV v4l-dvb repository; see <ulink
url="http://linuxtv.org/repo/">http://linuxtv.org/repo/</ulink> for
access instructions.</para>
<!-- Note for convenience vidioc-dbg-g-register.sgml
contains a duplicate of this table. -->
<table pgwide="1" frame="none" id="name-v4l2-dbg-match">
<title>struct <structname>v4l2_dbg_match</structname></title>
<tgroup cols="4">
&cs-ustr;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>type</structfield></entry>
<entry>See <xref linkend="name-chip-match-types" /> for a list of
possible types.</entry>
</row>
<row>
<entry>union</entry>
<entry>(anonymous)</entry>
</row>
<row>
<entry></entry>
<entry>__u32</entry>
<entry><structfield>addr</structfield></entry>
<entry>Match a chip by this number, interpreted according
to the <structfield>type</structfield> field.</entry>
</row>
<row>
<entry></entry>
<entry>char</entry>
<entry><structfield>name[32]</structfield></entry>
<entry>Match a chip by this name, interpreted according
to the <structfield>type</structfield> field.</entry>
</row>
</tbody>
</tgroup>
</table>
<table pgwide="1" frame="none" id="v4l2-dbg-chip-info">
<title>struct <structname>v4l2_dbg_chip_info</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>struct v4l2_dbg_match</entry>
<entry><structfield>match</structfield></entry>
<entry>How to match the chip, see <xref linkend="name-v4l2-dbg-match" />.</entry>
</row>
<row>
<entry>char</entry>
<entry><structfield>name[32]</structfield></entry>
<entry>The name of the chip.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>flags</structfield></entry>
<entry>Set by the driver. If <constant>V4L2_CHIP_FL_READABLE</constant>
is set, then the driver supports reading registers from the device. If
<constant>V4L2_CHIP_FL_WRITABLE</constant> is set, then it supports writing registers.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>reserved[8]</structfield></entry>
<entry>Reserved fields, both application and driver must set these to 0.</entry>
</row>
</tbody>
</tgroup>
</table>
<!-- Note for convenience vidioc-dbg-g-register.sgml
contains a duplicate of this table. -->
<table pgwide="1" frame="none" id="name-chip-match-types">
<title>Chip Match Types</title>
<tgroup cols="3">
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_CHIP_MATCH_BRIDGE</constant></entry>
<entry>0</entry>
<entry>Match the nth chip on the card, zero for the
bridge chip. Does not match sub-devices.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_I2C_DRIVER</constant></entry>
<entry>1</entry>
<entry>Match an &i2c; chip by its driver name. Can't be used with this ioctl.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_I2C_ADDR</constant></entry>
<entry>2</entry>
<entry>Match a chip by its 7 bit &i2c; bus address. Can't be used with this ioctl.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_AC97</constant></entry>
<entry>3</entry>
<entry>Match the nth anciliary AC97 chip. Can't be used with this ioctl.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_SUBDEV</constant></entry>
<entry>4</entry>
<entry>Match the nth sub-device.</entry>
</row>
</tbody>
</tgroup>
</table>
</refsect1>
<refsect1>
&return-value;
<variablelist>
<varlistentry>
<term><errorcode>EINVAL</errorcode></term>
<listitem>
<para>The <structfield>match_type</structfield> is invalid or
no device could be matched.</para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
</refentry>

29
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View File

@ -87,7 +87,7 @@ written into the register.</para>
<para>To read a register applications must initialize the
<structfield>match.type</structfield>,
<structfield>match.chip</structfield> or <structfield>match.name</structfield> and
<structfield>match.addr</structfield> or <structfield>match.name</structfield> and
<structfield>reg</structfield> fields, and call
<constant>VIDIOC_DBG_G_REGISTER</constant> with a pointer to this
structure. On success the driver stores the register value in the
@ -95,11 +95,11 @@ structure. On success the driver stores the register value in the
unchanged.</para>
<para>When <structfield>match.type</structfield> is
<constant>V4L2_CHIP_MATCH_HOST</constant>,
<structfield>match.addr</structfield> selects the nth non-&i2c; chip
<constant>V4L2_CHIP_MATCH_BRIDGE</constant>,
<structfield>match.addr</structfield> selects the nth non-sub-device chip
on the TV card. The number zero always selects the host chip, &eg; the
chip connected to the PCI or USB bus. You can find out which chips are
present with the &VIDIOC-DBG-G-CHIP-IDENT; ioctl.</para>
present with the &VIDIOC-DBG-G-CHIP-INFO; ioctl.</para>
<para>When <structfield>match.type</structfield> is
<constant>V4L2_CHIP_MATCH_I2C_DRIVER</constant>,
@ -109,7 +109,7 @@ For instance
supported by the saa7127 driver, regardless of its &i2c; bus address.
When multiple chips supported by the same driver are present, the
effect of these ioctls is undefined. Again with the
&VIDIOC-DBG-G-CHIP-IDENT; ioctl you can find out which &i2c; chips are
&VIDIOC-DBG-G-CHIP-INFO; ioctl you can find out which &i2c; chips are
present.</para>
<para>When <structfield>match.type</structfield> is
@ -122,19 +122,23 @@ bus address.</para>
<structfield>match.addr</structfield> selects the nth AC97 chip
on the TV card.</para>
<para>When <structfield>match.type</structfield> is
<constant>V4L2_CHIP_MATCH_SUBDEV</constant>,
<structfield>match.addr</structfield> selects the nth sub-device.</para>
<note>
<title>Success not guaranteed</title>
<para>Due to a flaw in the Linux &i2c; bus driver these ioctls may
return successfully without actually reading or writing a register. To
catch the most likely failure we recommend a &VIDIOC-DBG-G-CHIP-IDENT;
catch the most likely failure we recommend a &VIDIOC-DBG-G-CHIP-INFO;
call confirming the presence of the selected &i2c; chip.</para>
</note>
<para>These ioctls are optional, not all drivers may support them.
However when a driver supports these ioctls it must also support
&VIDIOC-DBG-G-CHIP-IDENT;. Conversely it may support
<constant>VIDIOC_DBG_G_CHIP_IDENT</constant> but not these ioctls.</para>
&VIDIOC-DBG-G-CHIP-INFO;. Conversely it may support
<constant>VIDIOC_DBG_G_CHIP_INFO</constant> but not these ioctls.</para>
<para><constant>VIDIOC_DBG_G_REGISTER</constant> and
<constant>VIDIOC_DBG_S_REGISTER</constant> were introduced in Linux
@ -217,10 +221,10 @@ register.</entry>
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_CHIP_MATCH_HOST</constant></entry>
<entry><constant>V4L2_CHIP_MATCH_BRIDGE</constant></entry>
<entry>0</entry>
<entry>Match the nth chip on the card, zero for the
host chip. Does not match &i2c; chips.</entry>
bridge chip. Does not match sub-devices.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_I2C_DRIVER</constant></entry>
@ -237,6 +241,11 @@ register.</entry>
<entry>3</entry>
<entry>Match the nth anciliary AC97 chip.</entry>
</row>
<row>
<entry><constant>V4L2_CHIP_MATCH_SUBDEV</constant></entry>
<entry>4</entry>
<entry>Match the nth sub-device.</entry>
</row>
</tbody>
</tgroup>
</table>

240
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View File

@ -1,240 +0,0 @@
<refentry id="vidioc-enum-dv-presets">
<refmeta>
<refentrytitle>ioctl VIDIOC_ENUM_DV_PRESETS</refentrytitle>
&manvol;
</refmeta>
<refnamediv>
<refname>VIDIOC_ENUM_DV_PRESETS</refname>
<refpurpose>Enumerate supported Digital Video presets</refpurpose>
</refnamediv>
<refsynopsisdiv>
<funcsynopsis>
<funcprototype>
<funcdef>int <function>ioctl</function></funcdef>
<paramdef>int <parameter>fd</parameter></paramdef>
<paramdef>int <parameter>request</parameter></paramdef>
<paramdef>struct v4l2_dv_enum_preset *<parameter>argp</parameter></paramdef>
</funcprototype>
</funcsynopsis>
</refsynopsisdiv>
<refsect1>
<title>Arguments</title>
<variablelist>
<varlistentry>
<term><parameter>fd</parameter></term>
<listitem>
<para>&fd;</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>request</parameter></term>
<listitem>
<para>VIDIOC_ENUM_DV_PRESETS</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>argp</parameter></term>
<listitem>
<para></para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
<refsect1>
<title>Description</title>
<para>This ioctl is <emphasis role="bold">deprecated</emphasis>.
New drivers and applications should use &VIDIOC-ENUM-DV-TIMINGS; instead.
</para>
<para>To query the attributes of a DV preset, applications initialize the
<structfield>index</structfield> field and zero the reserved array of &v4l2-dv-enum-preset;
and call the <constant>VIDIOC_ENUM_DV_PRESETS</constant> ioctl with a pointer to this
structure. Drivers fill the rest of the structure or return an
&EINVAL; when the index is out of bounds. To enumerate all DV Presets supported,
applications shall begin at index zero, incrementing by one until the
driver returns <errorcode>EINVAL</errorcode>. Drivers may enumerate a
different set of DV presets after switching the video input or
output.</para>
<table pgwide="1" frame="none" id="v4l2-dv-enum-preset">
<title>struct <structname>v4l2_dv_enum_presets</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>index</structfield></entry>
<entry>Number of the DV preset, set by the
application.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>preset</structfield></entry>
<entry>This field identifies one of the DV preset values listed in <xref linkend="v4l2-dv-presets-vals"/>.</entry>
</row>
<row>
<entry>__u8</entry>
<entry><structfield>name</structfield>[24]</entry>
<entry>Name of the preset, a NUL-terminated ASCII string, for example: "720P-60", "1080I-60". This information is
intended for the user.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>width</structfield></entry>
<entry>Width of the active video in pixels for the DV preset.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>height</structfield></entry>
<entry>Height of the active video in lines for the DV preset.</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>reserved</structfield>[4]</entry>
<entry>Reserved for future extensions. Drivers must set the array to zero.</entry>
</row>
</tbody>
</tgroup>
</table>
<table pgwide="1" frame="none" id="v4l2-dv-presets-vals">
<title>struct <structname>DV Presets</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>Preset</entry>
<entry>Preset value</entry>
<entry>Description</entry>
</row>
<row>
<entry></entry>
<entry></entry>
<entry></entry>
</row>
<row>
<entry>V4L2_DV_INVALID</entry>
<entry>0</entry>
<entry>Invalid preset value.</entry>
</row>
<row>
<entry>V4L2_DV_480P59_94</entry>
<entry>1</entry>
<entry>720x480 progressive video at 59.94 fps as per BT.1362.</entry>
</row>
<row>
<entry>V4L2_DV_576P50</entry>
<entry>2</entry>
<entry>720x576 progressive video at 50 fps as per BT.1362.</entry>
</row>
<row>
<entry>V4L2_DV_720P24</entry>
<entry>3</entry>
<entry>1280x720 progressive video at 24 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_720P25</entry>
<entry>4</entry>
<entry>1280x720 progressive video at 25 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_720P30</entry>
<entry>5</entry>
<entry>1280x720 progressive video at 30 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_720P50</entry>
<entry>6</entry>
<entry>1280x720 progressive video at 50 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_720P59_94</entry>
<entry>7</entry>
<entry>1280x720 progressive video at 59.94 fps as per SMPTE 274M.</entry>
</row>
<row>
<entry>V4L2_DV_720P60</entry>
<entry>8</entry>
<entry>1280x720 progressive video at 60 fps as per SMPTE 274M/296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080I29_97</entry>
<entry>9</entry>
<entry>1920x1080 interlaced video at 29.97 fps as per BT.1120/SMPTE 274M.</entry>
</row>
<row>
<entry>V4L2_DV_1080I30</entry>
<entry>10</entry>
<entry>1920x1080 interlaced video at 30 fps as per BT.1120/SMPTE 274M.</entry>
</row>
<row>
<entry>V4L2_DV_1080I25</entry>
<entry>11</entry>
<entry>1920x1080 interlaced video at 25 fps as per BT.1120.</entry>
</row>
<row>
<entry>V4L2_DV_1080I50</entry>
<entry>12</entry>
<entry>1920x1080 interlaced video at 50 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080I60</entry>
<entry>13</entry>
<entry>1920x1080 interlaced video at 60 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080P24</entry>
<entry>14</entry>
<entry>1920x1080 progressive video at 24 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080P25</entry>
<entry>15</entry>
<entry>1920x1080 progressive video at 25 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080P30</entry>
<entry>16</entry>
<entry>1920x1080 progressive video at 30 fps as per SMPTE 296M.</entry>
</row>
<row>
<entry>V4L2_DV_1080P50</entry>
<entry>17</entry>
<entry>1920x1080 progressive video at 50 fps as per BT.1120.</entry>
</row>
<row>
<entry>V4L2_DV_1080P60</entry>
<entry>18</entry>
<entry>1920x1080 progressive video at 60 fps as per BT.1120.</entry>
</row>
</tbody>
</tgroup>
</table>
</refsect1>
<refsect1>
&return-value;
<variablelist>
<varlistentry>
<term><errorcode>EINVAL</errorcode></term>
<listitem>
<para>The &v4l2-dv-enum-preset; <structfield>index</structfield>
is out of bounds.</para>
</listitem>
</varlistentry>
<varlistentry>
<term><errorcode>ENODATA</errorcode></term>
<listitem>
<para>Digital video presets are not supported for this input or output.</para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
</refentry>

5
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View File

@ -277,11 +277,6 @@ input/output interface to linux-media@vger.kernel.org on 19 Oct 2009.
<tgroup cols="3">
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_IN_CAP_PRESETS</constant></entry>
<entry>0x00000001</entry>
<entry>This input supports setting DV presets by using VIDIOC_S_DV_PRESET.</entry>
</row>
<row>
<entry><constant>V4L2_IN_CAP_DV_TIMINGS</constant></entry>
<entry>0x00000002</entry>

5
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View File

@ -162,11 +162,6 @@ input/output interface to linux-media@vger.kernel.org on 19 Oct 2009.
<tgroup cols="3">
&cs-def;
<tbody valign="top">
<row>
<entry><constant>V4L2_OUT_CAP_PRESETS</constant></entry>
<entry>0x00000001</entry>
<entry>This output supports setting DV presets by using VIDIOC_S_DV_PRESET.</entry>
</row>
<row>
<entry><constant>V4L2_OUT_CAP_DV_TIMINGS</constant></entry>
<entry>0x00000002</entry>

113
Documentation/DocBook/media/v4l/vidioc-g-dv-preset.xml
View File

@ -1,113 +0,0 @@
<refentry id="vidioc-g-dv-preset">
<refmeta>
<refentrytitle>ioctl VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET</refentrytitle>
&manvol;
</refmeta>
<refnamediv>
<refname>VIDIOC_G_DV_PRESET</refname>
<refname>VIDIOC_S_DV_PRESET</refname>
<refpurpose>Query or select the DV preset of the current input or output</refpurpose>
</refnamediv>
<refsynopsisdiv>
<funcsynopsis>
<funcprototype>
<funcdef>int <function>ioctl</function></funcdef>
<paramdef>int <parameter>fd</parameter></paramdef>
<paramdef>int <parameter>request</parameter></paramdef>
<paramdef>struct v4l2_dv_preset *<parameter>argp</parameter></paramdef>
</funcprototype>
</funcsynopsis>
</refsynopsisdiv>
<refsect1>
<title>Arguments</title>
<variablelist>
<varlistentry>
<term><parameter>fd</parameter></term>
<listitem>
<para>&fd;</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>request</parameter></term>
<listitem>
<para>VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>argp</parameter></term>
<listitem>
<para></para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
<refsect1>
<title>Description</title>
<para>These ioctls are <emphasis role="bold">deprecated</emphasis>.
New drivers and applications should use &VIDIOC-G-DV-TIMINGS; and &VIDIOC-S-DV-TIMINGS;
instead.
</para>
<para>To query and select the current DV preset, applications
use the <constant>VIDIOC_G_DV_PRESET</constant> and <constant>VIDIOC_S_DV_PRESET</constant>
ioctls which take a pointer to a &v4l2-dv-preset; type as argument.
Applications must zero the reserved array in &v4l2-dv-preset;.
<constant>VIDIOC_G_DV_PRESET</constant> returns a dv preset in the field
<structfield>preset</structfield> of &v4l2-dv-preset;.</para>
<para><constant>VIDIOC_S_DV_PRESET</constant> accepts a pointer to a &v4l2-dv-preset;
that has the preset value to be set. Applications must zero the reserved array in &v4l2-dv-preset;.
If the preset is not supported, it returns an &EINVAL; </para>
</refsect1>
<refsect1>
&return-value;
<variablelist>
<varlistentry>
<term><errorcode>EINVAL</errorcode></term>
<listitem>
<para>This ioctl is not supported, or the
<constant>VIDIOC_S_DV_PRESET</constant>,<constant>VIDIOC_S_DV_PRESET</constant> parameter was unsuitable.</para>
</listitem>
</varlistentry>
<varlistentry>
<term><errorcode>ENODATA</errorcode></term>
<listitem>
<para>Digital video presets are not supported for this input or output.</para>
</listitem>
</varlistentry>
<varlistentry>
<term><errorcode>EBUSY</errorcode></term>
<listitem>
<para>The device is busy and therefore can not change the preset.</para>
</listitem>
</varlistentry>
</variablelist>
<table pgwide="1" frame="none" id="v4l2-dv-preset">
<title>struct <structname>v4l2_dv_preset</structname></title>
<tgroup cols="3">
&cs-str;
<tbody valign="top">
<row>
<entry>__u32</entry>
<entry><structfield>preset</structfield></entry>
<entry>Preset value to represent the digital video timings</entry>
</row>
<row>
<entry>__u32</entry>
<entry><structfield>reserved[4]</structfield></entry>
<entry>Reserved fields for future use</entry>
</row>
</tbody>
</tgroup>
</table>
</refsect1>
</refentry>

9
Documentation/DocBook/media/v4l/vidioc-g-ext-ctrls.xml
View File

@ -319,6 +319,15 @@ These controls are described in <xref
processing controls. These controls are described in <xref
linkend="image-process-controls" />.</entry>
</row>
<row>
<entry><constant>V4L2_CTRL_CLASS_FM_RX</constant></entry>
<entry>0xa10000</entry>
<entry>The class containing FM Receiver (FM RX) controls.
These controls are described in <xref
linkend="fm-rx-controls" />.</entry>
</row>
</tbody>
</tgroup>
</table>

78
Documentation/DocBook/media/v4l/vidioc-query-dv-preset.xml
View File

@ -1,78 +0,0 @@
<refentry id="vidioc-query-dv-preset">
<refmeta>
<refentrytitle>ioctl VIDIOC_QUERY_DV_PRESET</refentrytitle>
&manvol;
</refmeta>
<refnamediv>
<refname>VIDIOC_QUERY_DV_PRESET</refname>
<refpurpose>Sense the DV preset received by the current
input</refpurpose>
</refnamediv>
<refsynopsisdiv>
<funcsynopsis>
<funcprototype>
<funcdef>int <function>ioctl</function></funcdef>
<paramdef>int <parameter>fd</parameter></paramdef>
<paramdef>int <parameter>request</parameter></paramdef>
<paramdef>struct v4l2_dv_preset *<parameter>argp</parameter></paramdef>
</funcprototype>
</funcsynopsis>
</refsynopsisdiv>
<refsect1>
<title>Arguments</title>
<variablelist>
<varlistentry>
<term><parameter>fd</parameter></term>
<listitem>
<para>&fd;</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>request</parameter></term>
<listitem>
<para>VIDIOC_QUERY_DV_PRESET</para>
</listitem>
</varlistentry>
<varlistentry>
<term><parameter>argp</parameter></term>
<listitem>
<para></para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
<refsect1>
<title>Description</title>
<para>This ioctl is <emphasis role="bold">deprecated</emphasis>.
New drivers and applications should use &VIDIOC-QUERY-DV-TIMINGS; instead.
</para>
<para>The hardware may be able to detect the current DV preset
automatically, similar to sensing the video standard. To do so, applications
call <constant> VIDIOC_QUERY_DV_PRESET</constant> with a pointer to a
&v4l2-dv-preset; type. Once the hardware detects a preset, that preset is
returned in the preset field of &v4l2-dv-preset;. If the preset could not be
detected because there was no signal, or the signal was unreliable, or the
signal did not map to a supported preset, then the value V4L2_DV_INVALID is
returned.</para>
</refsect1>
<refsect1>
&return-value;
<variablelist>
<varlistentry>
<term><errorcode>ENODATA</errorcode></term>
<listitem>
<para>Digital video presets are not supported for this input or output.</para>
</listitem>
</varlistentry>
</variablelist>
</refsect1>
</refentry>

1
Documentation/DocBook/media_api.tmpl
View File

@ -23,6 +23,7 @@
<!-- LinuxTV v4l-dvb repository. -->
<!ENTITY v4l-dvb "<ulink url='http://linuxtv.org/repo/'>http://linuxtv.org/repo/</ulink>">
<!ENTITY dash-ent-10 "<entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry>">
<!ENTITY dash-ent-16 "<entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry><entry>-</entry>">
]>
<book id="media_api">

44
Documentation/EDID/1600x1200.S 100644
View File

@ -0,0 +1,44 @@
/*
1600x1200.S: EDID data set for standard 1600x1200 60 Hz monitor
Copyright (C) 2013 Carsten Emde <C.Emde@osadl.org>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* EDID */
#define VERSION 1
#define REVISION 3
/* Display */
#define CLOCK 162000 /* kHz */
#define XPIX 1600
#define YPIX 1200
#define XY_RATIO XY_RATIO_4_3
#define XBLANK 560
#define YBLANK 50
#define XOFFSET 64
#define XPULSE 192
#define YOFFSET (63+1)
#define YPULSE (63+3)
#define DPI 72
#define VFREQ 60 /* Hz */
#define TIMING_NAME "Linux UXGA"
#define ESTABLISHED_TIMINGS_BITS 0x00 /* none */
#define HSYNC_POL 1
#define VSYNC_POL 1
#define CRC 0x9d
#include "edid.S"

12
Documentation/EDID/HOWTO.txt
View File

@ -18,12 +18,12 @@ CONFIG_DRM_LOAD_EDID_FIRMWARE was introduced. It allows to provide an
individually prepared or corrected EDID data set in the /lib/firmware
directory from where it is loaded via the firmware interface. The code
(see drivers/gpu/drm/drm_edid_load.c) contains built-in data sets for
commonly used screen resolutions (1024x768, 1280x1024, 1680x1050,
1920x1080) as binary blobs, but the kernel source tree does not contain
code to create these data. In order to elucidate the origin of the
built-in binary EDID blobs and to facilitate the creation of individual
data for a specific misbehaving monitor, commented sources and a
Makefile environment are given here.
commonly used screen resolutions (1024x768, 1280x1024, 1600x1200,
1680x1050, 1920x1080) as binary blobs, but the kernel source tree does
not contain code to create these data. In order to elucidate the origin
of the built-in binary EDID blobs and to facilitate the creation of
individual data for a specific misbehaving monitor, commented sources
and a Makefile environment are given here.
To create binary EDID and C source code files from the existing data
material, simply type "make".

9
Documentation/SubmittingPatches
View File

@ -420,7 +420,7 @@ person it names. This tag documents that potentially interested parties
have been included in the discussion
14) Using Reported-by:, Tested-by: and Reviewed-by:
14) Using Reported-by:, Tested-by:, Reviewed-by: and Suggested-by:
If this patch fixes a problem reported by somebody else, consider adding a
Reported-by: tag to credit the reporter for their contribution. Please
@ -468,6 +468,13 @@ done on the patch. Reviewed-by: tags, when supplied by reviewers known to
understand the subject area and to perform thorough reviews, will normally
increase the likelihood of your patch getting into the kernel.
A Suggested-by: tag indicates that the patch idea is suggested by the person
named and ensures credit to the person for the idea. Please note that this
tag should not be added without the reporter's permission, especially if the
idea was not posted in a public forum. That said, if we diligently credit our
idea reporters, they will, hopefully, be inspired to help us again in the
future.
15) The canonical patch format

56
Documentation/arm/sunxi/clocks.txt 100644
View File

@ -0,0 +1,56 @@
Frequently asked questions about the sunxi clock system
=======================================================
This document contains useful bits of information that people tend to ask
about the sunxi clock system, as well as accompanying ASCII art when adequate.
Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
system?
A: The 24MHz oscillator allows gating to save power. Indeed, if gated
carelessly the system would stop functioning, but with the right
steps, one can gate it and keep the system running. Consider this
simplified suspend example:
While the system is operational, you would see something like
24MHz 32kHz
|
PLL1
\
\_ CPU Mux
|
[CPU]
When you are about to suspend, you switch the CPU Mux to the 32kHz
oscillator:
24Mhz 32kHz
| |
PLL1 |
/
CPU Mux _/
|
[CPU]
Finally you can gate the main oscillator
32kHz
|
|
/
CPU Mux _/
|
[CPU]
Q: Were can I learn more about the sunxi clocks?
A: The linux-sunxi wiki contains a page documenting the clock registers,
you can find it at
http://linux-sunxi.org/A10/CCM
The authoritative source for information at this time is the ccmu driver
released by Allwinner, you can find it at
https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu

7
Documentation/backlight/lp855x-driver.txt
View File

@ -32,14 +32,10 @@ Platform data for lp855x
For supporting platform specific data, the lp855x platform data can be used.
* name : Backlight driver name. If it is not defined, default name is set.
* mode : Brightness control mode. PWM or register based.
* device_control : Value of DEVICE CONTROL register.
* initial_brightness : Initial value of backlight brightness.
* period_ns : Platform specific PWM period value. unit is nano.
Only valid when brightness is pwm input mode.
* load_new_rom_data :
0 : use default configuration data
1 : update values of eeprom or eprom registers on loading driver
* size_program : Total size of lp855x_rom_data.
* rom_data : List of new eeprom/eprom registers.
@ -54,10 +50,8 @@ static struct lp855x_rom_data lp8552_eeprom_arr[] = {
static struct lp855x_platform_data lp8552_pdata = {
.name = "lcd-bl",
.mode = REGISTER_BASED,
.device_control = I2C_CONFIG(LP8552),
.initial_brightness = INITIAL_BRT,
.load_new_rom_data = 1,
.size_program = ARRAY_SIZE(lp8552_eeprom_arr),
.rom_data = lp8552_eeprom_arr,
};
@ -65,7 +59,6 @@ static struct lp855x_platform_data lp8552_pdata = {
example 2) lp8556 platform data : pwm input mode with default rom data
static struct lp855x_platform_data lp8556_pdata = {
.mode = PWM_BASED,
.device_control = PWM_CONFIG(LP8556),
.initial_brightness = INITIAL_BRT,
.period_ns = 1000000,

2
Documentation/cgroups/00-INDEX
View File

@ -18,6 +18,8 @@ memcg_test.txt
- Memory Resource Controller; implementation details.
memory.txt
- Memory Resource Controller; design, accounting, interface, testing.
net_cls.txt
- Network classifier cgroups details and usages.
net_prio.txt
- Network priority cgroups details and usages.
resource_counter.txt

3
Documentation/cgroups/cgroups.txt
View File

@ -442,7 +442,7 @@ You can attach the current shell task by echoing 0:
You can use the cgroup.procs file instead of the tasks file to move all
threads in a threadgroup at once. Echoing the PID of any task in a
threadgroup to cgroup.procs causes all tasks in that threadgroup to be
be attached to the cgroup. Writing 0 to cgroup.procs moves all tasks
attached to the cgroup. Writing 0 to cgroup.procs moves all tasks
in the writing task's threadgroup.
Note: Since every task is always a member of exactly one cgroup in each
@ -580,6 +580,7 @@ propagation along the hierarchy. See the comment on
cgroup_for_each_descendant_pre() for details.
void css_offline(struct cgroup *cgrp);
(cgroup_mutex held by caller)
This is the counterpart of css_online() and called iff css_online()
has succeeded on @cgrp. This signifies the beginning of the end of

70
Documentation/cgroups/devices.txt
View File

@ -13,9 +13,7 @@ either an integer or * for all. Access is a composition of r
The root device cgroup starts with rwm to 'all'. A child device
cgroup gets a copy of the parent. Administrators can then remove
devices from the whitelist or add new entries. A child cgroup can
never receive a device access which is denied by its parent. However
when a device access is removed from a parent it will not also be
removed from the child(ren).
never receive a device access which is denied by its parent.
2. User Interface
@ -50,3 +48,69 @@ task to a new cgroup. (Again we'll probably want to change that).
A cgroup may not be granted more permissions than the cgroup's
parent has.
4. Hierarchy
device cgroups maintain hierarchy by making sure a cgroup never has more
access permissions than its parent. Every time an entry is written to
a cgroup's devices.deny file, all its children will have that entry removed
from their whitelist and all the locally set whitelist entries will be
re-evaluated. In case one of the locally set whitelist entries would provide
more access than the cgroup's parent, it'll be removed from the whitelist.
Example:
A
/ \
B
group behavior exceptions
A allow "b 8:* rwm", "c 116:1 rw"
B deny "c 1:3 rwm", "c 116:2 rwm", "b 3:* rwm"
If a device is denied in group A:
# echo "c 116:* r" > A/devices.deny
it'll propagate down and after revalidating B's entries, the whitelist entry
"c 116:2 rwm" will be removed:
group whitelist entries denied devices
A all "b 8:* rwm", "c 116:* rw"
B "c 1:3 rwm", "b 3:* rwm" all the rest
In case parent's exceptions change and local exceptions are not allowed
anymore, they'll be deleted.
Notice that new whitelist entries will not be propagated:
A
/ \
B
group whitelist entries denied devices
A "c 1:3 rwm", "c 1:5 r" all the rest
B "c 1:3 rwm", "c 1:5 r" all the rest
when adding "c *:3 rwm":
# echo "c *:3 rwm" >A/devices.allow
the result:
group whitelist entries denied devices
A "c *:3 rwm", "c 1:5 r" all the rest
B "c 1:3 rwm", "c 1:5 r" all the rest
but now it'll be possible to add new entries to B:
# echo "c 2:3 rwm" >B/devices.allow
# echo "c 50:3 r" >B/devices.allow
or even
# echo "c *:3 rwm" >B/devices.allow
Allowing or denying all by writing 'a' to devices.allow or devices.deny will
not be possible once the device cgroups has children.
4.1 Hierarchy (internal implementation)
device cgroups is implemented internally using a behavior (ALLOW, DENY) and a
list of exceptions. The internal state is controlled using the same user
interface to preserve compatibility with the previous whitelist-only
implementation. Removal or addition of exceptions that will reduce the access
to devices will be propagated down the hierarchy.
For every propagated exception, the effective rules will be re-evaluated based
on current parent's access rules.

72
Documentation/cgroups/memory.txt
View File

@ -40,6 +40,7 @@ Features:
- soft limit
- moving (recharging) account at moving a task is selectable.
- usage threshold notifier
- memory pressure notifier
- oom-killer disable knob and oom-notifier
- Root cgroup has no limit controls.
@ -65,6 +66,7 @@ Brief summary of control files.
memory.stat # show various statistics
memory.use_hierarchy # set/show hierarchical account enabled
memory.force_empty # trigger forced move charge to parent
memory.pressure_level # set memory pressure notifications
memory.swappiness # set/show swappiness parameter of vmscan
(See sysctl's vm.swappiness)
memory.move_charge_at_immigrate # set/show controls of moving charges
@ -194,7 +196,7 @@ the cgroup that brought it in -- this will happen on memory pressure).
But see section 8.2: when moving a task to another cgroup, its pages may
be recharged to the new cgroup, if move_charge_at_immigrate has been chosen.
Exception: If CONFIG_CGROUP_CGROUP_MEMCG_SWAP is not used.
Exception: If CONFIG_MEMCG_SWAP is not used.
When you do swapoff and make swapped-out pages of shmem(tmpfs) to
be backed into memory in force, charges for pages are accounted against the
caller of swapoff rather than the users of shmem.
@ -762,7 +764,73 @@ At reading, current status of OOM is shown.
under_oom 0 or 1 (if 1, the memory cgroup is under OOM, tasks may
be stopped.)
11. TODO
11. Memory Pressure
The pressure level notifications can be used to monitor the memory
allocation cost; based on the pressure, applications can implement
different strategies of managing their memory resources. The pressure
levels are defined as following:
The "low" level means that the system is reclaiming memory for new
allocations. Monitoring this reclaiming activity might be useful for
maintaining cache level. Upon notification, the program (typically
"Activity Manager") might analyze vmstat and act in advance (i.e.
prematurely shutdown unimportant services).
The "medium" level means that the system is experiencing medium memory
pressure, the system might be making swap, paging out active file caches,
etc. Upon this event applications may decide to further analyze
vmstat/zoneinfo/memcg or internal memory usage statistics and free any
resources that can be easily reconstructed or re-read from a disk.
The "critical" level means that the system is actively thrashing, it is
about to out of memory (OOM) or even the in-kernel OOM killer is on its
way to trigger. Applications should do whatever they can to help the
system. It might be too late to consult with vmstat or any other
statistics, so it's advisable to take an immediate action.
The events are propagated upward until the event is handled, i.e. the
events are not pass-through. Here is what this means: for example you have
three cgroups: A->B->C. Now you set up an event listener on cgroups A, B
and C, and suppose group C experiences some pressure. In this situation,
only group C will receive the notification, i.e. groups A and B will not
receive it. This is done to avoid excessive "broadcasting" of messages,
which disturbs the system and which is especially bad if we are low on
memory or thrashing. So, organize the cgroups wisely, or propagate the
events manually (or, ask us to implement the pass-through events,
explaining why would you need them.)
The file memory.pressure_level is only used to setup an eventfd. To
register a notification, an application must:
- create an eventfd using eventfd(2);
- open memory.pressure_level;
- write string like "<event_fd> <fd of memory.pressure_level> <level>"
to cgroup.event_control.
Application will be notified through eventfd when memory pressure is at
the specific level (or higher). Read/write operations to
memory.pressure_level are no implemented.
Test:
Here is a small script example that makes a new cgroup, sets up a
memory limit, sets up a notification in the cgroup and then makes child
cgroup experience a critical pressure:
# cd /sys/fs/cgroup/memory/
# mkdir foo
# cd foo
# cgroup_event_listener memory.pressure_level low &
# echo 8000000 > memory.limit_in_bytes
# echo 8000000 > memory.memsw.limit_in_bytes
# echo $$ > tasks
# dd if=/dev/zero | read x
(Expect a bunch of notifications, and eventually, the oom-killer will
trigger.)
12. TODO
1. Add support for accounting huge pages (as a separate controller)
2. Make per-cgroup scanner reclaim not-shared pages first

34
Documentation/cgroups/net_cls.txt 100644
View File

@ -0,0 +1,34 @@
Network classifier cgroup
-------------------------
The Network classifier cgroup provides an interface to
tag network packets with a class identifier (classid).
The Traffic Controller (tc) can be used to assign
different priorities to packets from different cgroups.
Creating a net_cls cgroups instance creates a net_cls.classid file.
This net_cls.classid value is initialized to 0.
You can write hexadecimal values to net_cls.classid; the format for these
values is 0xAAAABBBB; AAAA is the major handle number and BBBB
is the minor handle number.
Reading net_cls.classid yields a decimal result.
Example:
mkdir /sys/fs/cgroup/net_cls
mount -t cgroup -onet_cls net_cls /sys/fs/cgroup/net_cls
mkdir /sys/fs/cgroup/net_cls/0
echo 0x100001 > /sys/fs/cgroup/net_cls/0/net_cls.classid
- setting a 10:1 handle.
cat /sys/fs/cgroup/net_cls/0/net_cls.classid
1048577
configuring tc:
tc qdisc add dev eth0 root handle 10: htb
tc class add dev eth0 parent 10: classid 10:1 htb rate 40mbit
- creating traffic class 10:1
tc filter add dev eth0 parent 10: protocol ip prio 10 handle 1: cgroup

15
Documentation/clk.txt
View File

@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
};
Below is a matrix detailing which clk_ops are mandatory based upon the
hardware capbilities of that clock. A cell marked as "y" means
hardware capabilities of that clock. A cell marked as "y" means
mandatory, a cell marked as "n" implies that either including that
callback is invalid or otherwise uneccesary. Empty cells are either
callback is invalid or otherwise unnecessary. Empty cells are either
optional or must be evaluated on a case-by-case basis.
clock hardware characteristics
@ -231,3 +231,14 @@ To better enforce this policy, always follow this simple rule: any
statically initialized clock data MUST be defined in a separate file
from the logic that implements its ops. Basically separate the logic
from the data and all is well.
Part 6 - Disabling clock gating of unused clocks
Sometimes during development it can be useful to be able to bypass the
default disabling of unused clocks. For example, if drivers aren't enabling
clocks properly but rely on them being on from the bootloader, bypassing
the disabling means that the driver will remain functional while the issues
are sorted out.
To bypass this disabling, include "clk_ignore_unused" in the bootargs to the
kernel.

9
Documentation/cpu-freq/cpu-drivers.txt
View File

@ -108,8 +108,9 @@ policy->governor must contain the "default policy" for
cpufreq_driver.target is called with
these values.
For setting some of these values, the frequency table helpers might be
helpful. See the section 2 for more information on them.
For setting some of these values (cpuinfo.min[max]_freq, policy->min[max]), the
frequency table helpers might be helpful. See the section 2 for more information
on them.
SMP systems normally have same clock source for a group of cpus. For these the
.init() would be called only once for the first online cpu. Here the .init()
@ -184,10 +185,10 @@ the reference implementation in drivers/cpufreq/longrun.c
As most cpufreq processors only allow for being set to a few specific
frequencies, a "frequency table" with some functions might assist in
some work of the processor driver. Such a "frequency table" consists
of an array of struct cpufreq_freq_table entries, with any value in
of an array of struct cpufreq_frequency_table entries, with any value in
"index" you want to use, and the corresponding frequency in
"frequency". At the end of the table, you need to add a
cpufreq_freq_table entry with frequency set to CPUFREQ_TABLE_END. And
cpufreq_frequency_table entry with frequency set to CPUFREQ_TABLE_END. And
if you want to skip one entry in the table, set the frequency to
CPUFREQ_ENTRY_INVALID. The entries don't need to be in ascending
order.

27
Documentation/cpu-freq/governors.txt
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@ -167,6 +167,27 @@ of load evaluation and helping the CPU stay at its top speed when truly
busy, rather than shifting back and forth in speed. This tunable has no
effect on behavior at lower speeds/lower CPU loads.
powersave_bias: this parameter takes a value between 0 to 1000. It
defines the percentage (times 10) value of the target frequency that
will be shaved off of the target. For example, when set to 100 -- 10%,
when ondemand governor would have targeted 1000 MHz, it will target
1000 MHz - (10% of 1000 MHz) = 900 MHz instead. This is set to 0
(disabled) by default.
When AMD frequency sensitivity powersave bias driver --
drivers/cpufreq/amd_freq_sensitivity.c is loaded, this parameter
defines the workload frequency sensitivity threshold in which a lower
frequency is chosen instead of ondemand governor's original target.
The frequency sensitivity is a hardware reported (on AMD Family 16h
Processors and above) value between 0 to 100% that tells software how
the performance of the workload running on a CPU will change when
frequency changes. A workload with sensitivity of 0% (memory/IO-bound)
will not perform any better on higher core frequency, whereas a
workload with sensitivity of 100% (CPU-bound) will perform better
higher the frequency. When the driver is loaded, this is set to 400
by default -- for CPUs running workloads with sensitivity value below
40%, a lower frequency is chosen. Unloading the driver or writing 0
will disable this feature.
2.5 Conservative
----------------
@ -191,6 +212,12 @@ governor but for the opposite direction. For example when set to its
default value of '20' it means that if the CPU usage needs to be below
20% between samples to have the frequency decreased.
sampling_down_factor: similar functionality as in "ondemand" governor.
But in "conservative", it controls the rate at which the kernel makes
a decision on when to decrease the frequency while running in any
speed. Load for frequency increase is still evaluated every
sampling rate.
3. The Governor Interface in the CPUfreq Core
=============================================

6
Documentation/cpuidle/driver.txt
View File

@ -15,11 +15,17 @@ has mechanisms in place to support actual entry-exit into CPU idle states.
cpuidle driver initializes the cpuidle_device structure for each CPU device
and registers with cpuidle using cpuidle_register_device.
If all the idle states are the same, the wrapper function cpuidle_register
could be used instead.
It can also support the dynamic changes (like battery <-> AC), by using
cpuidle_pause_and_lock, cpuidle_disable_device and cpuidle_enable_device,
cpuidle_resume_and_unlock.
Interfaces:
extern int cpuidle_register(struct cpuidle_driver *drv,
const struct cpumask *const coupled_cpus);
extern int cpuidle_unregister(struct cpuidle_driver *drv);
extern int cpuidle_register_driver(struct cpuidle_driver *drv);
extern void cpuidle_unregister_driver(struct cpuidle_driver *drv);
extern int cpuidle_register_device(struct cpuidle_device *dev);

82
Documentation/device-mapper/dm-raid.txt
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@ -1,10 +1,13 @@
dm-raid
-------
=======
The device-mapper RAID (dm-raid) target provides a bridge from DM to MD.
It allows the MD RAID drivers to be accessed using a device-mapper
interface.
Mapping Table Interface
-----------------------
The target is named "raid" and it accepts the following parameters:
<raid_type> <#raid_params> <raid_params> \
@ -47,7 +50,7 @@ The target is named "raid" and it accepts the following parameters:
followed by optional parameters (in any order):
[sync|nosync] Force or prevent RAID initialization.
[rebuild <idx>] Rebuild drive number idx (first drive is 0).
[rebuild <idx>] Rebuild drive number 'idx' (first drive is 0).
[daemon_sleep <ms>]
Interval between runs of the bitmap daemon that
@ -56,9 +59,9 @@ The target is named "raid" and it accepts the following parameters:
[min_recovery_rate <kB/sec/disk>] Throttle RAID initialization
[max_recovery_rate <kB/sec/disk>] Throttle RAID initialization
[write_mostly <idx>] Drive index is write-mostly
[max_write_behind <sectors>] See '-write-behind=' (man mdadm)
[stripe_cache <sectors>] Stripe cache size (higher RAIDs only)
[write_mostly <idx>] Mark drive index 'idx' write-mostly.
[max_write_behind <sectors>] See '--write-behind=' (man mdadm)
[stripe_cache <sectors>] Stripe cache size (RAID 4/5/6 only)
[region_size <sectors>]
The region_size multiplied by the number of regions is the
logical size of the array. The bitmap records the device
@ -122,7 +125,7 @@ The target is named "raid" and it accepts the following parameters:
given for both the metadata and data drives for a given position.
Example tables
Example Tables
--------------
# RAID4 - 4 data drives, 1 parity (no metadata devices)
# No metadata devices specified to hold superblock/bitmap info
@ -141,26 +144,70 @@ Example tables
raid4 4 2048 sync min_recovery_rate 20 \
5 8:17 8:18 8:33 8:34 8:49 8:50 8:65 8:66 8:81 8:82
Status Output
-------------
'dmsetup table' displays the table used to construct the mapping.
The optional parameters are always printed in the order listed
above with "sync" or "nosync" always output ahead of the other
arguments, regardless of the order used when originally loading the table.
Arguments that can be repeated are ordered by value.
'dmsetup status' yields information on the state and health of the
array.
The output is as follows:
'dmsetup status' yields information on the state and health of the array.
The output is as follows (normally a single line, but expanded here for
clarity):
1: <s> <l> raid \
2: <raid_type> <#devices> <1 health char for each dev> <resync_ratio>
2: <raid_type> <#devices> <health_chars> \
3: <sync_ratio> <sync_action> <mismatch_cnt>
Line 1 is the standard output produced by device-mapper.
Line 2 is produced by the raid target, and best explained by example:
0 1960893648 raid raid4 5 AAAAA 2/490221568
Line 2 & 3 are produced by the raid target and are best explained by example:
0 1960893648 raid raid4 5 AAAAA 2/490221568 init 0
Here we can see the RAID type is raid4, there are 5 devices - all of
which are 'A'live, and the array is 2/490221568 complete with recovery.
Faulty or missing devices are marked 'D'. Devices that are out-of-sync
are marked 'a'.
which are 'A'live, and the array is 2/490221568 complete with its initial
recovery. Here is a fuller description of the individual fields:
<raid_type> Same as the <raid_type> used to create the array.
<health_chars> One char for each device, indicating: 'A' = alive and
in-sync, 'a' = alive but not in-sync, 'D' = dead/failed.
<sync_ratio> The ratio indicating how much of the array has undergone
the process described by 'sync_action'. If the
'sync_action' is "check" or "repair", then the process
of "resync" or "recover" can be considered complete.
<sync_action> One of the following possible states:
idle - No synchronization action is being performed.
frozen - The current action has been halted.
resync - Array is undergoing its initial synchronization
or is resynchronizing after an unclean shutdown
(possibly aided by a bitmap).
recover - A device in the array is being rebuilt or
replaced.
check - A user-initiated full check of the array is
being performed. All blocks are read and
checked for consistency. The number of
discrepancies found are recorded in
<mismatch_cnt>. No changes are made to the
array by this action.
repair - The same as "check", but discrepancies are
corrected.
reshape - The array is undergoing a reshape.
<mismatch_cnt> The number of discrepancies found between mirror copies
in RAID1/10 or wrong parity values found in RAID4/5/6.
This value is valid only after a "check" of the array
is performed. A healthy array has a 'mismatch_cnt' of 0.
Message Interface
-----------------
The dm-raid target will accept certain actions through the 'message' interface.
('man dmsetup' for more information on the message interface.) These actions
include:
"idle" - Halt the current sync action.
"frozen" - Freeze the current sync action.
"resync" - Initiate/continue a resync.
"recover"- Initiate/continue a recover process.
"check" - Initiate a check (i.e. a "scrub") of the array.
"repair" - Initiate a repair of the array.
"reshape"- Currently unsupported (-EINVAL).
Version History
---------------
@ -171,4 +218,7 @@ Version History
1.3.1 Allow device replacement/rebuild for RAID 10
1.3.2 Fix/improve redundancy checking for RAID10
1.4.0 Non-functional change. Removes arg from mapping function.
1.4.1 Add RAID10 "far" and "offset" algorithm support.
1.4.1 RAID10 fix redundancy validation checks (commit 55ebbb5).
1.4.2 Add RAID10 "far" and "offset" algorithm support.
1.5.0 Add message interface to allow manipulation of the sync_action.
New status (STATUSTYPE_INFO) fields: sync_action and mismatch_cnt.

11
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@ -0,0 +1,11 @@
Altera SOCFPGA Clock Manager
Required properties:
- compatible : "altr,clk-mgr"
- reg : Should contain base address and length for Clock Manager
Example:
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
};

13
Documentation/devicetree/bindings/arm/atmel-adc.txt
View File

@ -14,9 +14,19 @@ Required properties:
- atmel,adc-status-register: Offset of the Interrupt Status Register
- atmel,adc-trigger-register: Offset of the Trigger Register
- atmel,adc-vref: Reference voltage in millivolts for the conversions
- atmel,adc-res: List of resolution in bits supported by the ADC. List size
must be two at least.
- atmel,adc-res-names: Contains one identifier string for each resolution
in atmel,adc-res property. "lowres" and "highres"
identifiers are required.
Optional properties:
- atmel,adc-use-external: Boolean to enable of external triggers
- atmel,adc-use-res: String corresponding to an identifier from
atmel,adc-res-names property. If not specified, the highest
resolution will be used.
- atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion
- atmel,adc-sample-hold-time: Sample and Hold Time in microseconds
Optional trigger Nodes:
- Required properties:
@ -40,6 +50,9 @@ adc0: adc@fffb0000 {
atmel,adc-trigger-register = <0x08>;
atmel,adc-use-external;
atmel,adc-vref = <3300>;
atmel,adc-res = <8 10>;
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "lowres";
trigger@0 {
trigger-name = "external-rising";

19
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@ -0,0 +1,19 @@
Broadcom Kona Family timer
-----------------------------------------------------
This timer is used in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
Required properties:
- compatible : "bcm,kona-timer"
- reg : Register range for the timer
- interrupts : interrupt for the timer
- clock-frequency: frequency that the clock operates
Example:
timer@35006000 {
compatible = "bcm,kona-timer";
reg = <0x35006000 0x1000>;
interrupts = <0x0 7 0x4>;
clock-frequency = <32768>;
};

18
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@ -0,0 +1,18 @@
* Qualcomm SSBI
Some Qualcomm MSM devices contain a point-to-point serial bus used to
communicate with a limited range of devices (mostly power management
chips).
These require the following properties:
- compatible: "qcom,ssbi"
- qcom,controller-type
indicates the SSBI bus variant the controller should use to talk
with the slave device. This should be one of "ssbi", "ssbi2", or
"pmic-arbiter". The type chosen is determined by the attached
slave.
The slave device should be the single child node of the ssbi device
with a compatible field.

41
Documentation/devicetree/bindings/arm/msm/timer.txt
View File

@ -3,36 +3,35 @@
Properties:
- compatible : Should at least contain "qcom,msm-timer". More specific
properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
purpose timer and a debug timer respectively.
properties specify which subsystem the timers are paired with.
- interrupts : Interrupt indicating a match event.
"qcom,kpss-timer" - krait subsystem
"qcom,scss-timer" - scorpion subsystem
- reg : Specifies the base address of the timer registers. The second region
specifies an optional register used to configure the clock divider.
- interrupts : Interrupts for the the debug timer, the first general purpose
timer, and optionally a second general purpose timer in that
order.
- clock-frequency : The frequency of the timer in Hz.
- reg : Specifies the base address of the timer registers.
- clock-frequency : The frequency of the debug timer and the general purpose
timer(s) in Hz in that order.
Optional:
- cpu-offset : per-cpu offset used when the timer is accessed without the
CPU remapping facilities. The offset is cpu-offset * cpu-nr.
CPU remapping facilities. The offset is
cpu-offset + (0x10000 * cpu-nr).
Example:
timer@200a004 {
compatible = "qcom,msm-gpt", "qcom,msm-timer";
interrupts = <1 2 0x301>;
reg = <0x0200a004 0x10>;
clock-frequency = <32768>;
cpu-offset = <0x40000>;
};
timer@200a024 {
compatible = "qcom,msm-dgt", "qcom,msm-timer";
interrupts = <1 3 0x301>;
reg = <0x0200a024 0x10>,
<0x0200a034 0x4>;
clock-frequency = <6750000>;
timer@200a000 {
compatible = "qcom,scss-timer", "qcom,msm-timer";
interrupts = <1 1 0x301>,
<1 2 0x301>,
<1 3 0x301>;
reg = <0x0200a000 0x100>;
clock-frequency = <19200000>,
<32768>;
cpu-offset = <0x40000>;
};

60
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@ -0,0 +1,60 @@
Samsung Exynos Analog to Digital Converter bindings
The devicetree bindings are for the new ADC driver written for
Exynos4 and upward SoCs from Samsung.
New driver handles the following
1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
and future SoCs from Samsung
2. Add ADC driver under iio/adc framework
3. Also adds the Documentation for device tree bindings
Required properties:
- compatible: Must be "samsung,exynos-adc-v1"
for exynos4412/5250 controllers.
Must be "samsung,exynos-adc-v2" for
future controllers.
- reg: Contains ADC register address range (base address and
length) and the address of the phy enable register.
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
- #io-channel-cells = <1>; As ADC has multiple outputs
- clocks From common clock binding: handle to adc clock.
- clock-names From common clock binding: Shall be "adc".
- vdd-supply VDD input supply.
Note: child nodes can be added for auto probing from device tree.
Example: adding device info in dtsi file
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>, <0x10040718 0x4>;
interrupts = <0 106 0>;
#io-channel-cells = <1>;
io-channel-ranges;
clocks = <&clock 303>;
clock-names = "adc";
vdd-supply = <&buck5_reg>;
};
Example: Adding child nodes in dts file
adc@12D10000 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
compatible = "ntc,ncp15wb473";
pullup-uV = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 4>;
};
};
Note: Does not apply to ADC driver under arch/arm/plat-samsung/
Note: The child node can be added under the adc node or separately.

67
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@ -1,19 +1,84 @@
NVIDIA Tegra Power Management Controller (PMC)
Properties:
The PMC block interacts with an external Power Management Unit. The PMC
mostly controls the entry and exit of the system from different sleep
modes. It provides power-gating controllers for SoC and CPU power-islands.
Required properties:
- name : Should be pmc
- compatible : Should contain "nvidia,tegra<chip>-pmc".
- reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pclk" (The Tegra clock of that name),
"clk32k_in" (The 32KHz clock input to Tegra).
Optional properties:
- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
The PMU is an external Power Management Unit, whose interrupt output
signal is fed into the PMC. This signal is optionally inverted, and then
fed into the ARM GIC. The PMC is not involved in the detection or
handling of this interrupt signal, merely its inversion.
- nvidia,suspend-mode : The suspend mode that the platform should use.
Valid values are 0, 1 and 2:
0 (LP0): CPU + Core voltage off and DRAM in self-refresh
1 (LP1): CPU voltage off and DRAM in self-refresh
2 (LP2): CPU voltage off
- nvidia,core-power-req-active-high : Boolean, core power request active-high
- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
is enabled.
Required properties when nvidia,suspend-mode is specified:
- nvidia,cpu-pwr-good-time : CPU power good time in uS.
- nvidia,cpu-pwr-off-time : CPU power off time in uS.
- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
Core power good time in uS.
- nvidia,core-pwr-off-time : Core power off time in uS.
Required properties when nvidia,suspend-mode=<0>:
- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
The LP0 vector contains the warm boot code that is executed by AVP when
resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
processor and always being the first boot processor when chip is power on
or resume from deep sleep mode. When the system is resumed from the deep
sleep mode, the warm boot code will restore some PLLs, clocks and then
bring up CPU0 for resuming the system.
Example:
/ SoC dts including file
pmc@7000f400 {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
clocks = <&tegra_car 110>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
nvidia,invert-interrupt;
nvidia,suspend-mode = <1>;
nvidia,cpu-pwr-good-time = <2000>;
nvidia,cpu-pwr-off-time = <100>;
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <458>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
nvidia,lp0-vec = <0xbdffd000 0x2000>;
};
/ Tegra board dts file
{
...
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clock {
compatible = "fixed-clock";
reg=<0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
...
};

17
Documentation/devicetree/bindings/ata/imx-pata.txt 100644
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@ -0,0 +1,17 @@
* Freescale i.MX PATA Controller
Required properties:
- compatible: "fsl,imx27-pata"
- reg: Address range of the PATA Controller
- interrupts: The interrupt of the PATA Controller
- clocks: the clocks for the PATA Controller
Example:
pata: pata@83fe0000 {
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 161>;
status = "disabled";
};

18
Documentation/devicetree/bindings/clock/altr_socfpga.txt 100644
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@ -0,0 +1,18 @@
Device Tree Clock bindings for Altera's SoCFPGA platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"altr,socfpga-pll-clock" - for a PLL clock
"altr,socfpga-perip-clock" - The peripheral clock divided from the
PLL clock.
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- clocks : shall be the input parent clock phandle for the clock. This is
either an oscillator or a pll output.
- #clock-cells : from common clock binding, shall be set to 0.
Optional properties:
- fixed-divider : If clocks have a fixed divider value, use this property.

22
Documentation/devicetree/bindings/clock/axi-clkgen.txt 100644
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@ -0,0 +1,22 @@
Binding for the axi-clkgen clock generator
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "adi,axi-clkgen".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
- clocks : Phandle and clock specifier for the parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock@0xff000000 {
compatible = "adi,axi-clkgen";
#clock-cells = <0>;
reg = <0xff000000 0x1000>;
clocks = <&osc 1>;
};

24
Documentation/devicetree/bindings/clock/fixed-factor-clock.txt 100644
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@ -0,0 +1,24 @@
Binding for simple fixed factor rate clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clock-div: fixed divider.
- clock-mult: fixed multiplier.
- clocks: parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock {
compatible = "fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
div = <2>;
mult = <1>;
};

117
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@ -0,0 +1,117 @@
* Clock bindings for Freescale i.MX27
Required properties:
- compatible: Should be "fsl,imx27-ccm"
- reg: Address and length of the register set
- interrupts: Should contain CCM interrupt
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. The following is a full list of i.MX27
clocks and IDs.
Clock ID
-----------------------
dummy 0
ckih 1
ckil 2
mpll 3
spll 4
mpll_main2 5
ahb 6
ipg 7
nfc_div 8
per1_div 9
per2_div 10
per3_div 11
per4_div 12
vpu_sel 13
vpu_div 14
usb_div 15
cpu_sel 16
clko_sel 17
cpu_div 18
clko_div 19
ssi1_sel 20
ssi2_sel 21
ssi1_div 22
ssi2_div 23
clko_en 24
ssi2_ipg_gate 25
ssi1_ipg_gate 26
slcdc_ipg_gate 27
sdhc3_ipg_gate 28
sdhc2_ipg_gate 29
sdhc1_ipg_gate 30
scc_ipg_gate 31
sahara_ipg_gate 32
rtc_ipg_gate 33
pwm_ipg_gate 34
owire_ipg_gate 35
lcdc_ipg_gate 36
kpp_ipg_gate 37
iim_ipg_gate 38
i2c2_ipg_gate 39
i2c1_ipg_gate 40
gpt6_ipg_gate 41
gpt5_ipg_gate 42
gpt4_ipg_gate 43
gpt3_ipg_gate 44
gpt2_ipg_gate 45
gpt1_ipg_gate 46
gpio_ipg_gate 47
fec_ipg_gate 48
emma_ipg_gate 49
dma_ipg_gate 50
cspi3_ipg_gate 51
cspi2_ipg_gate 52
cspi1_ipg_gate 53
nfc_baud_gate 54
ssi2_baud_gate 55
ssi1_baud_gate 56
vpu_baud_gate 57
per4_gate 58
per3_gate 59
per2_gate 60
per1_gate 61
usb_ahb_gate 62
slcdc_ahb_gate 63
sahara_ahb_gate 64
lcdc_ahb_gate 65
vpu_ahb_gate 66
fec_ahb_gate 67
emma_ahb_gate 68
emi_ahb_gate 69
dma_ahb_gate 70
csi_ahb_gate 71
brom_ahb_gate 72
ata_ahb_gate 73
wdog_ipg_gate 74
usb_ipg_gate 75
uart6_ipg_gate 76
uart5_ipg_gate 77
uart4_ipg_gate 78
uart3_ipg_gate 79
uart2_ipg_gate 80
uart1_ipg_gate 81
ckih_div1p5 82
fpm 83
mpll_osc_sel 84
mpll_sel 85
Examples:
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
interrupts = <20>;
clocks = <&clks 81>, <&clks 61>;
clock-names = "ipg", "per";
status = "disabled";
};

114
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@ -0,0 +1,114 @@
Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
The Si5351a/b/c are programmable i2c clock generators with upto 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
3 output clocks are accessible. The internal structure of the clock
generators can be found in [1].
==I2C device node==
Required properties:
- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
handles, shall be xtal reference clock or xtal and clkin for
si5351c only.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
Optional properties:
- silabs,pll-source: pair of (number, source) for each pll. Allows
to overwrite clock source of pll A (number=0) or B (number=1).
==Child nodes==
Each of the clock outputs can be overwritten individually by
using a child node to the I2C device node. If a child node for a clock
output is not set, the eeprom configuration is not overwritten.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- silabs,clock-source: source clock of the output divider stage N, shall be
0 = multisynth N
1 = multisynth 0 for output clocks 0-3, else multisynth4
2 = xtal
3 = clkin (si5351c only)
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
==Example==
/* 25MHz reference crystal */
ref25: ref25M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* Si5351a msop10 i2c clock generator */
si5351a: clock-generator@60 {
compatible = "silabs,si5351a-msop";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* connect xtal input to 25MHz reference */
clocks = <&ref25>;
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
/*
* overwrite clkout0 configuration with:
* - 8mA output drive strength
* - pll0 as clock source of multisynth0
* - multisynth0 as clock source of output divider
* - multisynth0 can change pll0
* - set initial clock frequency of 74.25MHz
*/
clkout0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,clock-source = <0>;
silabs,pll-master;
clock-frequency = <74250000>;
};
/*
* overwrite clkout1 configuration with:
* - 4mA output drive strength
* - pll1 as clock source of multisynth1
* - multisynth1 as clock source of output divider
* - multisynth1 can change pll1
*/
clkout1 {
reg = <1>;
silabs,drive-strength = <4>;
silabs,multisynth-source = <1>;
silabs,clock-source = <0>;
pll-master;
};
/*
* overwrite clkout2 configuration with:
* - xtal as clock source of output divider
*/
clkout2 {
reg = <2>;
silabs,clock-source = <2>;
};
};
};

151
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@ -0,0 +1,151 @@
Device Tree Clock bindings for arch-sunxi
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"allwinner,sun4i-osc-clk" - for a gatable oscillator
"allwinner,sun4i-pll1-clk" - for the main PLL clock
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,sun4i-*-gates-clk" where it shall be set to 1
Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls
For example:
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};
Gate clock outputs
The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
their corresponding offsets as present on sun4i are listed below. Note that
some of these gates are not present on sun5i.
* AXI gates ("allwinner,sun4i-axi-gates-clk")
DRAM 0
* AHB gates ("allwinner,sun4i-ahb-gates-clk")
USB0 0
EHCI0 1
OHCI0 2*
EHCI1 3
OHCI1 4*
SS 5
DMA 6
BIST 7
MMC0 8
MMC1 9
MMC2 10
MMC3 11
MS 12**
NAND 13
SDRAM 14
ACE 16
EMAC 17
TS 18
SPI0 20
SPI1 21
SPI2 22
SPI3 23
PATA 24
SATA 25**
GPS 26*
VE 32
TVD 33
TVE0 34
TVE1 35
LCD0 36
LCD1 37
CSI0 40
CSI1 41
HDMI 43
DE_BE0 44
DE_BE1 45
DE_FE0 46
DE_FE1 47
MP 50
MALI400 52
* APB0 gates ("allwinner,sun4i-apb0-gates-clk")
CODEC 0
SPDIF 1*
AC97 2
IIS 3
PIO 5
IR0 6
IR1 7
KEYPAD 10
* APB1 gates ("allwinner,sun4i-apb1-gates-clk")
I2C0 0
I2C1 1
I2C2 2
CAN 4
SCR 5
PS20 6
PS21 7
UART0 16
UART1 17
UART2 18
UART3 19
UART4 20
UART5 21
UART6 22
UART7 23
Notation:
[*]: The datasheet didn't mention these, but they are present on AW code
[**]: The datasheet had this marked as "NC" but they are used on AW code

65
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@ -0,0 +1,65 @@
Generic ARM big LITTLE cpufreq driver's DT glue
-----------------------------------------------
This is DT specific glue layer for generic cpufreq driver for big LITTLE
systems.
Both required and optional properties listed below must be defined
under node /cpus/cpu@x. Where x is the first cpu inside a cluster.
FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
must be present contiguously. Generic DT driver will check only node 'x' for
cpu:x.
Required properties:
- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
for details
Optional properties:
- clock-latency: Specify the possible maximum transition latency for clock,
in unit of nanoseconds.
Examples:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a15";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
792000 1100000
396000 950000
198000 850000
>;
clock-latency = <61036>; /* two CLK32 periods */
};
cpu@1 {
compatible = "arm,cortex-a15";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@100 {
compatible = "arm,cortex-a7";
reg = <100>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
792000 950000
396000 750000
198000 450000
>;
clock-latency = <61036>; /* two CLK32 periods */
};
cpu@101 {
compatible = "arm,cortex-a7";
reg = <101>;
next-level-cache = <&L2>;
};
};

2
Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
View File

@ -32,7 +32,7 @@ cpus {
396000 950000
198000 850000
>;
transition-latency = <61036>; /* two CLK32 periods */
clock-latency = <61036>; /* two CLK32 periods */
};
cpu@1 {

28
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@ -0,0 +1,28 @@
Exynos5440 cpufreq driver
-------------------
Exynos5440 SoC cpufreq driver for CPU frequency scaling.
Required properties:
- interrupts: Interrupt to know the completion of cpu frequency change.
- operating-points: Table of frequencies and voltage CPU could be transitioned into,
in the decreasing order. Frequency should be in KHz units and voltage
should be in microvolts.
Optional properties:
- clock-latency: Clock monitor latency in microsecond.
All the required listed above must be defined under node cpufreq.
Example:
--------
cpufreq@160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
interrupts = <0 57 0>;
operating-points = <
1000000 975000
800000 925000>;
clock-latency = <100000>;
};

15
Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt 100644
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@ -0,0 +1,15 @@
Freescale SAHARA Cryptographic Accelerator included in some i.MX chips.
Currently only i.MX27 is supported.
Required properties:
- compatible : Should be "fsl,<soc>-sahara"
- reg : Should contain SAHARA registers location and length
- interrupts : Should contain SAHARA interrupt number
Example:
sah@10025000 {
compatible = "fsl,imx27-sahara";
reg = < 0x10025000 0x800>;
interrupts = <75>;
};

22
Documentation/devicetree/bindings/drm/exynos/g2d.txt
View File

@ -1,22 +0,0 @@
Samsung 2D Graphic Accelerator using DRM frame work
Samsung FIMG2D is a graphics 2D accelerator which supports Bit Block Transfer.
We set the drawing-context registers for configuring rendering parameters and
then start rendering.
This driver is for SOCs which contain G2D IPs with version 4.1.
Required properties:
-compatible:
should be "samsung,exynos-g2d-41".
-reg:
physical base address of the controller and length
of memory mapped region.
-interrupts:
interrupt combiner values.
Example:
g2d {
compatible = "samsung,exynos-g2d-41";
reg = <0x10850000 0x1000>;
interrupts = <0 91 0>;
};

6
Documentation/devicetree/bindings/gpio/gpio.txt
View File

@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
}
@ -107,8 +107,8 @@ where,
Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
by this gpio controller.
pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
pinctrl2 with gpio offset 10 is handled by this gpio controller.
The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node.

29
Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt 100644
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@ -0,0 +1,29 @@
NTC Thermistor hwmon sensors
-------------------------------
Requires node properties:
- "compatible" value : one of
"ntc,ncp15wb473"
"ntc,ncp18wb473"
"ntc,ncp21wb473"
"ntc,ncp03wb473"
"ntc,ncp15wl333"
- "pullup-uv" Pull up voltage in micro volts
- "pullup-ohm" Pull up resistor value in ohms
- "pulldown-ohm" Pull down resistor value in ohms
- "connected-positive" Always ON, If not specified.
Status change is possible.
- "io-channels" Channel node of ADC to be used for
conversion.
Read more about iio bindings at
Documentation/devicetree/bindings/iio/iio-bindings.txt
Example:
ncp15wb473@0 {
compatible = "ntc,ncp15wb473";
pullup-uv = <1800000>;
pullup-ohm = <47000>;
pulldown-ohm = <0>;
io-channels = <&adc 3>;
};

18
Documentation/devicetree/bindings/hwrng/timeriomem_rng.txt 100644
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@ -0,0 +1,18 @@
HWRNG support for the timeriomem_rng driver
Required properties:
- compatible : "timeriomem_rng"
- reg : base address to sample from
- period : wait time in microseconds to use between samples
N.B. currently 'reg' must be four bytes wide and aligned
Example:
hwrng@44 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "timeriomem_rng";
reg = <0x44 0x04>;
period = <1000000>;
};

80
Documentation/devicetree/bindings/i2c/i2c-arb-gpio-challenge.txt 100644
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@ -0,0 +1,80 @@
GPIO-based I2C Arbitration Using a Challenge & Response Mechanism
=================================================================
This uses GPIO lines and a challenge & response mechanism to arbitrate who is
the master of an I2C bus in a multimaster situation.
In many cases using GPIOs to arbitrate is not needed and a design can use
the standard I2C multi-master rules. Using GPIOs is generally useful in
the case where there is a device on the bus that has errata and/or bugs
that makes standard multimaster mode not feasible.
Algorithm:
All masters on the bus have a 'bus claim' line which is an output that the
others can see. These are all active low with pull-ups enabled. We'll
describe these lines as:
- OUR_CLAIM: output from us signaling to other hosts that we want the bus
- THEIR_CLAIMS: output from others signaling that they want the bus
The basic algorithm is to assert your line when you want the bus, then make
sure that the other side doesn't want it also. A detailed explanation is best
done with an example.
Let's say we want to claim the bus. We:
1. Assert OUR_CLAIM.
2. Waits a little bit for the other sides to notice (slew time, say 10
microseconds).
3. Check THEIR_CLAIMS. If none are asserted then the we have the bus and we are
done.
4. Otherwise, wait for a few milliseconds and see if THEIR_CLAIMS are released.
5. If not, back off, release the claim and wait for a few more milliseconds.
6. Go back to 1 (until retry time has expired).
Required properties:
- compatible: i2c-arb-gpio-challenge
- our-claim-gpio: The GPIO that we use to claim the bus.
- their-claim-gpios: The GPIOs that the other sides use to claim the bus.
Note that some implementations may only support a single other master.
- Standard I2C mux properties. See mux.txt in this directory.
- Single I2C child bus node at reg 0. See mux.txt in this directory.
Optional properties:
- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us.
- wait-retry-us: we'll attempt another claim after this many microseconds.
Default is 3000 us.
- wait-free-us: we'll give up after this many microseconds. Default is 50000 us.
Example:
i2c@12CA0000 {
compatible = "acme,some-i2c-device";
#address-cells = <1>;
#size-cells = <0>;
};
i2c-arbitrator {
compatible = "i2c-arb-gpio-challenge";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&{/i2c@12CA0000}>;
our-claim-gpio = <&gpf0 3 1>;
their-claim-gpios = <&gpe0 4 1>;
slew-delay-us = <10>;
wait-retry-us = <3000>;
wait-free-us = <50000>;
i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
i2c@52 {
// Normal I2C device
};
};
};

2
Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
View File

@ -26,7 +26,7 @@ Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
- pinctrl-names: Should contain only one value - "default".
Optional properties:
- samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
- samsung,i2c-slave-addr: Slave address in multi-master environment. If not
specified, default value is 0.
- samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
specified, the default value in Hz is 100000.

2
Documentation/devicetree/bindings/i2c/trivial-devices.txt
View File

@ -35,6 +35,8 @@ fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface

97
Documentation/devicetree/bindings/iio/iio-bindings.txt 100644
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@ -0,0 +1,97 @@
This binding is derived from clock bindings, and based on suggestions
from Lars-Peter Clausen [1].
Sources of IIO channels can be represented by any node in the device
tree. Those nodes are designated as IIO providers. IIO consumer
nodes use a phandle and IIO specifier pair to connect IIO provider
outputs to IIO inputs. Similar to the gpio specifiers, an IIO
specifier is an array of one or more cells identifying the IIO
output on a device. The length of an IIO specifier is defined by the
value of a #io-channel-cells property in the IIO provider node.
[1] http://marc.info/?l=linux-iio&m=135902119507483&w=2
==IIO providers==
Required properties:
#io-channel-cells: Number of cells in an IIO specifier; Typically 0 for nodes
with a single IIO output and 1 for nodes with multiple
IIO outputs.
Example for a simple configuration with no trigger:
adc: voltage-sensor@35 {
compatible = "maxim,max1139";
reg = <0x35>;
#io-channel-cells = <1>;
};
Example for a configuration with trigger:
adc@35 {
compatible = "some-vendor,some-adc";
reg = <0x35>;
adc1: iio-device@0 {
#io-channel-cells = <1>;
/* other properties */
};
adc2: iio-device@1 {
#io-channel-cells = <1>;
/* other properties */
};
};
==IIO consumers==
Required properties:
io-channels: List of phandle and IIO specifier pairs, one pair
for each IIO input to the device. Note: if the
IIO provider specifies '0' for #io-channel-cells,
then only the phandle portion of the pair will appear.
Optional properties:
io-channel-names:
List of IIO input name strings sorted in the same
order as the io-channels property. Consumers drivers
will use io-channel-names to match IIO input names
with IIO specifiers.
io-channel-ranges:
Empty property indicating that child nodes can inherit named
IIO channels from this node. Useful for bus nodes to provide
and IIO channel to their children.
For example:
device {
io-channels = <&adc 1>, <&ref 0>;
io-channel-names = "vcc", "vdd";
};
This represents a device with two IIO inputs, named "vcc" and "vdd".
The vcc channel is connected to output 1 of the &adc device, and the
vdd channel is connected to output 0 of the &ref device.
==Example==
adc: max1139@35 {
compatible = "maxim,max1139";
reg = <0x35>;
#io-channel-cells = <1>;
};
...
iio_hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>,
<&adc 3>, <&adc 4>, <&adc 5>,
<&adc 6>, <&adc 7>, <&adc 8>,
<&adc 9>;
};
some_consumer {
compatible = "some-consumer";
io-channels = <&adc 10>, <&adc 11>;
io-channel-names = "adc1", "adc2";
};

16
Documentation/devicetree/bindings/input/ps2keyb-mouse-apbps2.txt 100644
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@ -0,0 +1,16 @@
Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
these properties are built from information in the AMBA plug&play and from
bootloader settings.
Required properties:
- name : Should be "GAISLER_APBPS2" or "01_060"
- reg : Address and length of the register set for the device
- interrupts : Interrupt numbers for this device
For further information look in the documentation for the GLIB IP core library:
http://www.gaisler.com/products/grlib/grip.pdf

30
Documentation/devicetree/bindings/input/touchscreen/auo_pixcir_ts.txt 100644
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@ -0,0 +1,30 @@
* AUO in-cell touchscreen controller using Pixcir sensors
Required properties:
- compatible: must be "auo,auo_pixcir_ts"
- reg: I2C address of the chip
- interrupts: interrupt to which the chip is connected
- gpios: gpios the chip is connected to
first one is the interrupt gpio and second one the reset gpio
- x-size: horizontal resolution of touchscreen
- y-size: vertical resolution of touchscreen
Example:
i2c@00000000 {
/* ... */
auo_pixcir_ts@5c {
compatible = "auo,auo_pixcir_ts";
reg = <0x5c>;
interrupts = <2 0>;
gpios = <&gpf 2 0 2>, /* INT */
<&gpf 5 1 0>; /* RST */
x-size = <800>;
y-size = <600>;
};
/* ... */
};

24
Documentation/devicetree/bindings/input/touchscreen/sitronix-st1232.txt 100644
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@ -0,0 +1,24 @@
* Sitronix st1232 touchscreen controller
Required properties:
- compatible: must be "sitronix,st1232"
- reg: I2C address of the chip
- interrupts: interrupt to which the chip is connected
Optional properties:
- gpios: a phandle to the reset GPIO
Example:
i2c@00000000 {
/* ... */
touchscreen@55 {
compatible = "sitronix,st1232";
reg = <0x55>;
interrupts = <2 0>;
gpios = <&gpio1 166 0>;
};
/* ... */
};

4
Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt → Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
View File

@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
Required properties:
- compatible : should be "allwinner,sunxi-ic"
- compatible : should be "allwinner,sun4i-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
@ -97,7 +97,7 @@ The interrupt sources are as follows:
Example:
intc: interrupt-controller {
compatible = "allwinner,sunxi-ic";
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
interrupt-controller;
#interrupt-cells = <2>;

2
Documentation/devicetree/bindings/leds/tca6507.txt
View File

@ -1,4 +1,4 @@
LEDs conected to tca6507
LEDs connected to tca6507
Required properties:
- compatible : should be : "ti,tca6507".

3
Documentation/devicetree/bindings/marvell.txt
View File

@ -115,6 +115,9 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
- compatible : "marvell,mv64360-eth-block"
- reg : Offset and length of the register set for this block
Optional properties:
- clocks : Phandle to the clock control device and gate bit
Example Discovery Ethernet block node:
ethernet-block@2000 {
#address-cells = <1>;

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Chips&Media Coda multi-standard codec IP
========================================
Coda codec IPs are present in i.MX SoCs in various versions,
called VPU (Video Processing Unit).
Required properties:
- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
(a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
(b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
(c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
- reg: should be register base and length as documented in the
SoC reference manual
- interrupts : Should contain the VPU interrupt. For CODA960,
a second interrupt is needed for the MJPEG unit.
- clocks : Should contain the ahb and per clocks, in the order
determined by the clock-names property.
- clock-names : Should be "ahb", "per"
- iram : phandle pointing to the SRAM device node
Example:
vpu: vpu@63ff4000 {
compatible = "fsl,imx53-vpu";
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks 63>, <&clks 63>;
clock-names = "ahb", "per";
iram = <&ocram>;
};

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Exynos4x12/Exynos5 SoC series camera host interface (FIMC-LITE)
Required properties:
- compatible : should be "samsung,exynos4212-fimc" for Exynos4212 and
Exynos4412 SoCs;
- reg : physical base address and size of the device memory mapped
registers;
- interrupts : should contain FIMC-LITE interrupt;
- clocks : FIMC LITE gate clock should be specified in this property.
- clock-names : should contain "flite" entry.
Each FIMC device should have an alias in the aliases node, in the form of
fimc-lite<n>, where <n> is an integer specifying the IP block instance.

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Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
The FIMC-IS is a subsystem for processing image signal from an image sensor.
The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
and SPI bus controllers, PWM and ADC.
fimc-is node
------------
Required properties:
- compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
Exynos4412 SoCs;
- reg : physical base address and length of the registers set;
- interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
- clocks : list of clock specifiers, corresponding to entries in
clock-names property;
- clock-names : must contain "ppmuispx", "ppmuispx", "lite0", "lite1"
"mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "uart",
"ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "aclk200",
"div_aclk200", "aclk400mcuisp", "div_aclk400mcuisp" entries,
matching entries in the clocks property.
pmu subnode
-----------
Required properties:
- reg : must contain PMU physical base address and size of the register set.
The following are the FIMC-IS peripheral device nodes and can be specified
either standalone or as the fimc-is node child nodes.
i2c-isp (ISP I2C bus controller) nodes
------------------------------------------
Required properties:
- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212 and
Exynos4412 SoCs;
- reg : physical base address and length of the registers set;
- clocks : must contain gate clock specifier for this controller;
- clock-names : must contain "i2c_isp" entry.
For the above nodes it is required to specify a pinctrl state named "default",
according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
Device tree nodes of the image sensors' controlled directly by the FIMC-IS
firmware must be child nodes of their corresponding ISP I2C bus controller node.
The data link of these image sensors must be specified using the common video
interfaces bindings, defined in video-interfaces.txt.

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Samsung S5P/EXYNOS SoC Camera Subsystem (FIMC)
----------------------------------------------
The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
represented by separate device tree nodes. Currently this includes: FIMC (in
the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
The sub-subdevices are defined as child nodes of the common 'camera' node which
also includes common properties of the whole subsystem not really specific to
any single sub-device, like common camera port pins or the CAMCLK clock outputs
for external image sensors attached to an SoC.
Common 'camera' node
--------------------
Required properties:
- compatible : must be "samsung,fimc", "simple-bus"
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property;
- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
"pxl_async1" entries, matching entries in the clocks property.
The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
to define a required pinctrl state named "default" and optional pinctrl states:
"idle", "active-a", active-b". These optional states can be used to switch the
camera port pinmux at runtime. The "idle" state should configure both the camera
ports A and B into high impedance state, especially the CAMCLK clock output
should be inactive. For the "active-a" state the camera port A must be activated
and the port B deactivated and for the state "active-b" it should be the other
way around.
The 'camera' node must include at least one 'fimc' child node.
'fimc' device nodes
-------------------
Required properties:
- compatible: "samsung,s5pv210-fimc" for S5PV210, "samsung,exynos4210-fimc"
for Exynos4210 and "samsung,exynos4212-fimc" for Exynos4x12 SoCs;
- reg: physical base address and length of the registers set for the device;
- interrupts: should contain FIMC interrupt;
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names;
- clock-names: must contain "fimc", "sclk_fimc" entries.
- samsung,pix-limits: an array of maximum supported image sizes in pixels, for
details refer to Table 2-1 in the S5PV210 SoC User Manual; The meaning of
each cell is as follows:
0 - scaler input horizontal size,
1 - input horizontal size for the scaler bypassed,
2 - REAL_WIDTH without input rotation,
3 - REAL_HEIGHT with input rotation,
- samsung,sysreg: a phandle to the SYSREG node.
Each FIMC device should have an alias in the aliases node, in the form of
fimc<n>, where <n> is an integer specifying the IP block instance.
Optional properties:
- clock-frequency: maximum FIMC local clock (LCLK) frequency;
- samsung,min-pix-sizes: an array specyfing minimum image size in pixels at
the FIMC input and output DMA, in the first and second cell respectively.
Default value when this property is not present is <16 16>;
- samsung,min-pix-alignment: minimum supported image height alignment (first
cell) and the horizontal image offset (second cell). The values are in pixels
and default to <2 1> when this property is not present;
- samsung,mainscaler-ext: a boolean property indicating whether the FIMC IP
supports extended image size and has CIEXTEN register;
- samsung,rotators: a bitmask specifying whether this IP has the input and
the output rotator. Bits 4 and 0 correspond to input and output rotator
respectively. If a rotator is present its corresponding bit should be set.
Default value when this property is not specified is 0x11.
- samsung,cam-if: a bolean property indicating whether the IP block includes
the camera input interface.
- samsung,isp-wb: this property must be present if the IP block has the ISP
writeback input.
- samsung,lcd-wb: this property must be present if the IP block has the LCD
writeback input.
'parallel-ports' node
---------------------
This node should contain child 'port' nodes specifying active parallel video
input ports. It includes camera A and camera B inputs. 'reg' property in the
port nodes specifies data input - 0, 1 indicates input A, B respectively.
Optional properties
- samsung,camclk-out : specifies clock output for remote sensor,
0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
Image sensor nodes
------------------
The sensor device nodes should be added to their control bus controller (e.g.
I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
using the common video interfaces bindings, defined in video-interfaces.txt.
The implementation of this bindings requires clock-frequency property to be
present in the sensor device nodes.
Example:
aliases {
fimc0 = &fimc_0;
};
/* Parallel bus IF sensor */
i2c_0: i2c@13860000 {
s5k6aa: sensor@3c {
compatible = "samsung,s5k6aafx";
reg = <0x3c>;
vddio-supply = <...>;
clock-frequency = <24000000>;
clocks = <...>;
clock-names = "mclk";
port {
s5k6aa_ep: endpoint {
remote-endpoint = <&fimc0_ep>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <1>;
pclk-sample = <1>;
};
};
};
};
/* MIPI CSI-2 bus IF sensor */
s5c73m3: sensor@0x1a {
compatible = "samsung,s5c73m3";
reg = <0x1a>;
vddio-supply = <...>;
clock-frequency = <24000000>;
clocks = <...>;
clock-names = "mclk";
port {
s5c73m3_1: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&csis0_ep>;
};
};
};
camera {
compatible = "samsung,fimc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cam_port_a_clk_active>;
/* parallel camera ports */
parallel-ports {
/* camera A input */
port@0 {
reg = <0>;
fimc0_ep: endpoint {
remote-endpoint = <&s5k6aa_ep>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <1>;
pclk-sample = <1>;
};
};
};
fimc_0: fimc@11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
interrupts = <0 85 0>;
status = "okay";
};
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x1000>;
interrupts = <0 78 0>;
/* camera C input */
port@3 {
reg = <3>;
csis0_ep: endpoint {
remote-endpoint = <&s5c73m3_ep>;
data-lanes = <1 2 3 4>;
samsung,csis-hs-settle = <12>;
};
};
};
};
The MIPI-CSIS device binding is defined in samsung-mipi-csis.txt.

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Samsung S5P/EXYNOS SoC series MIPI CSI-2 receiver (MIPI CSIS)
-------------------------------------------------------------
Required properties:
- compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
"samsung,exynos4210-csis" for Exynos4210 (S5PC210),
"samsung,exynos4212-csis" for Exynos4212/Exynos4412
SoC series;
- reg : offset and length of the register set for the device;
- interrupts : should contain MIPI CSIS interrupt; the format of the
interrupt specifier depends on the interrupt controller;
- bus-width : maximum number of data lanes supported (SoC specific);
- vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
- vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V);
- clocks : list of clock specifiers, corresponding to entries in
clock-names property;
- clock-names : must contain "csis", "sclk_csis" entries, matching entries
in the clocks property.
Optional properties:
- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
value when this property is not specified is 166 MHz;
- samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present
external clock from CMU will be used, or the bus clock if
if it's not specified.
The device node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in Documentation/devicetree/bindings/
media/video-interfaces.txt. The following are properties specific to those nodes.
port node
---------
- reg : (required) must be 3 for camera C input (CSIS0) or 4 for
camera D input (CSIS1);
endpoint node
-------------
- data-lanes : (required) an array specifying active physical MIPI-CSI2
data input lanes and their mapping to logical lanes; the
array's content is unused, only its length is meaningful;
- samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time;
Example:
reg0: regulator@0 {
};
reg1: regulator@1 {
};
/* SoC properties */
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x1000>;
interrupts = <0 78 0>;
#address-cells = <1>;
#size-cells = <0>;
};
/* Board properties */
csis_0: csis@11880000 {
clock-frequency = <166000000>;
vddio-supply = <&reg0>;
vddcore-supply = <&reg1>;
port {
reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */
csis0_ep: endpoint {
remote-endpoint = <...>;
data-lanes = <1>, <2>;
samsung,csis-hs-settle = <12>;
};
};
};

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Common bindings for video receiver and transmitter interfaces
General concept
---------------
Video data pipelines usually consist of external devices, e.g. camera sensors,
controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
video DMA engines and video data processors.
SoC internal blocks are described by DT nodes, placed similarly to other SoC
blocks. External devices are represented as child nodes of their respective
bus controller nodes, e.g. I2C.
Data interfaces on all video devices are described by their child 'port' nodes.
Configuration of a port depends on other devices participating in the data
transfer and is described by 'endpoint' subnodes.
device {
...
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
...
endpoint@0 { ... };
endpoint@1 { ... };
};
port@1 { ... };
};
};
If a port can be configured to work with more than one remote device on the same
bus, an 'endpoint' child node must be provided for each of them. If more than
one port is present in a device node or there is more than one endpoint at a
port, or port node needs to be associated with a selected hardware interface,
a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
used.
All 'port' nodes can be grouped under optional 'ports' node, which allows to
specify #address-cells, #size-cells properties independently for the 'port'
and 'endpoint' nodes and any child device nodes a device might have.
Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
phandles. An endpoint subnode of a device contains all properties needed for
configuration of this device for data exchange with other device. In most
cases properties at the peer 'endpoint' nodes will be identical, however they
might need to be different when there is any signal modifications on the bus
between two devices, e.g. there are logic signal inverters on the lines.
It is allowed for multiple endpoints at a port to be active simultaneously,
where supported by a device. For example, in case where a data interface of
a device is partitioned into multiple data busses, e.g. 16-bit input port
divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
and data-shift properties can be used to assign physical data lines to each
endpoint node (logical bus).
Required properties
-------------------
If there is more than one 'port' or more than one 'endpoint' node or 'reg'
property is present in port and/or endpoint nodes the following properties
are required in a relevant parent node:
- #address-cells : number of cells required to define port/endpoint
identifier, should be 1.
- #size-cells : should be zero.
Optional endpoint properties
----------------------------
- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
- slave-mode: a boolean property indicating that the link is run in slave mode.
The default when this property is not specified is master mode. In the slave
mode horizontal and vertical synchronization signals are provided to the
slave device (data source) by the master device (data sink). In the master
mode the data source device is also the source of the synchronization signals.
- bus-width: number of data lines actively used, valid for the parallel busses.
- data-shift: on the parallel data busses, if bus-width is used to specify the
number of data lines, data-shift can be used to specify which data lines are
used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
Note, that if HSYNC and VSYNC polarities are not specified, embedded
synchronization may be required, where supported.
- data-active: similar to HSYNC and VSYNC, specifies data line polarity.
- field-even-active: field signal level during the even field data transmission.
- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
signal.
- data-lanes: an array of physical data lane indexes. Position of an entry
determines the logical lane number, while the value of an entry indicates
physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
"data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
This property is valid for serial busses only (e.g. MIPI CSI-2).
- clock-lanes: an array of physical clock lane indexes. Position of an entry
determines the logical lane number, while the value of an entry indicates
physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
which places the clock lane on hardware lane 0. This property is valid for
serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
array contains only one entry.
- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
clock mode.
Example
-------
The example snippet below describes two data pipelines. ov772x and imx074 are
camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
Both sensors are on the I2C control bus corresponding to the i2c0 controller
node. ov772x sensor is linked directly to the ceu0 video host interface.
imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
(single) DMA engine writing captured data to memory. ceu0 node has a single
'port' node which may indicate that at any time only one of the following data
pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
ceu0: ceu@0xfe910000 {
compatible = "renesas,sh-mobile-ceu";
reg = <0xfe910000 0xa0>;
interrupts = <0x880>;
mclk: master_clock {
compatible = "renesas,ceu-clock";
#clock-cells = <1>;
clock-frequency = <50000000>; /* Max clock frequency */
clock-output-names = "mclk";
};
port {
#address-cells = <1>;
#size-cells = <0>;
/* Parallel bus endpoint */
ceu0_1: endpoint@1 {
reg = <1>; /* Local endpoint # */
remote = <&ov772x_1_1>; /* Remote phandle */
bus-width = <8>; /* Used data lines */
data-shift = <2>; /* Lines 9:2 are used */
/* If hsync-active/vsync-active are missing,
embedded BT.656 sync is used */
hsync-active = <0>; /* Active low */
vsync-active = <0>; /* Active low */
data-active = <1>; /* Active high */
pclk-sample = <1>; /* Rising */
};
/* MIPI CSI-2 bus endpoint */
ceu0_0: endpoint@0 {
reg = <0>;
remote = <&csi2_2>;
};
};
};
i2c0: i2c@0xfff20000 {
...
ov772x_1: camera@0x21 {
compatible = "omnivision,ov772x";
reg = <0x21>;
vddio-supply = <&regulator1>;
vddcore-supply = <&regulator2>;
clock-frequency = <20000000>;
clocks = <&mclk 0>;
clock-names = "xclk";
port {
/* With 1 endpoint per port no need for addresses. */
ov772x_1_1: endpoint {
bus-width = <8>;
remote-endpoint = <&ceu0_1>;
hsync-active = <1>;
vsync-active = <0>; /* Who came up with an
inverter here ?... */
data-active = <1>;
pclk-sample = <1>;
};
};
};
imx074: camera@0x1a {
compatible = "sony,imx074";
reg = <0x1a>;
vddio-supply = <&regulator1>;
vddcore-supply = <&regulator2>;
clock-frequency = <30000000>; /* Shared clock with ov772x_1 */
clocks = <&mclk 0>;
clock-names = "sysclk"; /* Assuming this is the
name in the datasheet */
port {
imx074_1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2>;
remote-endpoint = <&csi2_1>;
};
};
};
};
csi2: csi2@0xffc90000 {
compatible = "renesas,sh-mobile-csi2";
reg = <0xffc90000 0x1000>;
interrupts = <0x17a0>;
#address-cells = <1>;
#size-cells = <0>;
port@1 {
compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */
reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S,
PHY_M has port address 0,
is unused. */
csi2_1: endpoint {
clock-lanes = <0>;
data-lanes = <2 1>;
remote-endpoint = <&imx074_1>;
};
};
port@2 {
reg = <2>; /* port 2: link to the CEU */
csi2_2: endpoint {
remote-endpoint = <&ceu0_0>;
};
};
};

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@ -12,7 +12,7 @@ Required properties:
handle 32 interrupt sources).
- interrupt-controller: The presence of this property identifies the node
as an interupt controller. No property value shall be defined.
as an interrupt controller. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.

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@ -10,10 +10,40 @@ Optional properties:
- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
Sub-nodes:
- regulators : Contain the regulator nodes. The MC13892 regulators are
bound using their names as listed below with their registers and bits
for enabling.
- regulators : Contain the regulator nodes. The regulators are bound using
their names as listed below with their registers and bits for enabling.
MC13783 regulators:
sw1a : regulator SW1A (register 24, bit 0)
sw1b : regulator SW1B (register 25, bit 0)
sw2a : regulator SW2A (register 26, bit 0)
sw2b : regulator SW2B (register 27, bit 0)
sw3 : regulator SW3 (register 29, bit 20)
vaudio : regulator VAUDIO (register 32, bit 0)
viohi : regulator VIOHI (register 32, bit 3)
violo : regulator VIOLO (register 32, bit 6)
vdig : regulator VDIG (register 32, bit 9)
vgen : regulator VGEN (register 32, bit 12)
vrfdig : regulator VRFDIG (register 32, bit 15)
vrfref : regulator VRFREF (register 32, bit 18)
vrfcp : regulator VRFCP (register 32, bit 21)
vsim : regulator VSIM (register 33, bit 0)
vesim : regulator VESIM (register 33, bit 3)
vcam : regulator VCAM (register 33, bit 6)
vrfbg : regulator VRFBG (register 33, bit 9)
vvib : regulator VVIB (register 33, bit 11)
vrf1 : regulator VRF1 (register 33, bit 12)
vrf2 : regulator VRF2 (register 33, bit 15)
vmmc1 : regulator VMMC1 (register 33, bit 18)
vmmc2 : regulator VMMC2 (register 33, bit 21)
gpo1 : regulator GPO1 (register 34, bit 6)
gpo2 : regulator GPO2 (register 34, bit 8)
gpo3 : regulator GPO3 (register 34, bit 10)
gpo4 : regulator GPO4 (register 34, bit 12)
pwgt1spi : regulator PWGT1SPI (register 34, bit 15)
pwgt2spi : regulator PWGT2SPI (register 34, bit 16)
MC13892 regulators:
vcoincell : regulator VCOINCELL (register 13, bit 23)
sw1 : regulator SW1 (register 24, bit 0)
sw2 : regulator SW2 (register 25, bit 0)

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Generic on-chip SRAM
Simple IO memory regions to be managed by the genalloc API.
Required properties:
- compatible : mmio-sram
- reg : SRAM iomem address range
Example:
sram: sram@5c000000 {
compatible = "mmio-sram";
reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
};

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* TI Highspeed MMC host controller for DaVinci
The Highspeed MMC Host Controller on TI DaVinci family
provides an interface for MMC, SD and SDIO types of memory cards.
This file documents the properties used by the davinci_mmc driver.
Required properties:
- compatible:
Should be "ti,da830-mmc": for da830, da850, dm365
Should be "ti,dm355-mmc": for dm355, dm644x
Optional properties:
- bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
- max-frequency: Maximum operating clock frequency, default 25MHz.
- dmas: List of DMA specifiers with the controller specific format
as described in the generic DMA client binding. A tx and rx
specifier is required.
- dma-names: RX and TX DMA request names. These strings correspond
1:1 with the DMA specifiers listed in dmas.
Example:
mmc0: mmc@1c40000 {
compatible = "ti,da830-mmc",
reg = <0x40000 0x1000>;
interrupts = <16>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
dmas = <&edma 16
&edma 17>;
dma-names = "rx", "tx";
};

14
Documentation/devicetree/bindings/net/can/atmel-can.txt 100644
View File

@ -0,0 +1,14 @@
* AT91 CAN *
Required properties:
- compatible: Should be "atmel,at91sam9263-can" or "atmel,at91sam9x5-can"
- reg: Should contain CAN controller registers location and length
- interrupts: Should contain IRQ line for the CAN controller
Example:
can0: can@f000c000 {
compatbile = "atmel,at91sam9x5-can";
reg = <0xf000c000 0x300>;
interrupts = <40 4 5>
};

16
Documentation/devicetree/bindings/net/cpsw.txt
View File

@ -15,16 +15,22 @@ Required properties:
- mac_control : Specifies Default MAC control register content
for the specific platform
- slaves : Specifies number for slaves
- cpts_active_slave : Specifies the slave to use for time stamping
- active_slave : Specifies the slave to use for time stamping,
ethtool and SIOCGMIIPHY
- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds
- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds
- phy_id : Specifies slave phy id
- mac-address : Specifies slave MAC address
Optional properties:
- ti,hwmods : Must be "cpgmac0"
- no_bd_ram : Must be 0 or 1
- dual_emac : Specifies Switch to act as Dual EMAC
Slave Properties:
Required properties:
- phy_id : Specifies slave phy id
- mac-address : Specifies slave MAC address
Optional properties:
- dual_emac_res_vlan : Specifies VID to be used to segregate the ports
Note: "ti,hwmods" field is used to fetch the base address and irq
@ -47,7 +53,7 @@ Examples:
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
cpts_active_slave = <0>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {
@ -73,7 +79,7 @@ Examples:
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
cpts_active_slave = <0>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
cpsw_emac0: slave@0 {

91
Documentation/devicetree/bindings/net/dsa/dsa.txt 100644
View File

@ -0,0 +1,91 @@
Marvell Distributed Switch Architecture Device Tree Bindings
------------------------------------------------------------
Required properties:
- compatible : Should be "marvell,dsa"
- #address-cells : Must be 2, first cell is the address on the MDIO bus
and second cell is the address in the switch tree.
Second cell is used only when cascading/chaining.
- #size-cells : Must be 0
- dsa,ethernet : Should be a phandle to a valid Ethernet device node
- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node
Optionnal properties:
- interrupts : property with a value describing the switch
interrupt number (not supported by the driver)
A DSA node can contain multiple switch chips which are therefore child nodes of
the parent DSA node. The maximum number of allowed child nodes is 4
(DSA_MAX_SWITCHES).
Each of these switch child nodes should have the following required properties:
- reg : Describes the switch address on the MII bus
- #address-cells : Must be 1
- #size-cells : Must be 0
A switch may have multiple "port" children nodes
Each port children node must have the following mandatory properties:
- reg : Describes the port address in the switch
- label : Describes the label associated with this port, special
labels are "cpu" to indicate a CPU port and "dsa" to
indicate an uplink/downlink port.
Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.
Optionnal property:
- link : Should be a phandle to another switch's DSA port.
This property is only used when switches are being
chained/cascaded together.
Example:
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
interrupts = <10>;
dsa,ethernet = <&ethernet0>;
dsa,mii-bus = <&mii_bus0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <16 0>; /* MDIO address 16, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@5 {
reg = <5>;
label = "cpu";
};
switch0uplink: port@6 {
reg = <6>;
label = "dsa";
link = <&switch1uplink>;
};
};
switch@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <17 1>; /* MDIO address 17, switch 1 in tree */
switch1uplink: port@0 {
reg = <0>;
label = "dsa";
link = <&switch0uplink>;
};
};
};

4
Documentation/devicetree/bindings/net/marvell-orion-mdio.txt
View File

@ -9,6 +9,10 @@ Required properties:
- compatible: "marvell,orion-mdio"
- reg: address and length of the SMI register
Optional properties:
- interrupts: interrupt line number for the SMI error/done interrupt
- clocks: Phandle to the clock control device and gate bit
The child nodes of the MDIO driver are the individual PHY devices
connected to this MDIO bus. They must have a "reg" property given the
PHY address on the MDIO bus.

2
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
View File

@ -1,6 +1,6 @@
* Atmel AT91 Pinmux Controller
The AT91 Pinmux Controler, enables the IC
The AT91 Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
8 muxing options (called periph modes). Since different modules require

2
Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt
View File

@ -5,7 +5,7 @@ controller, and pinmux/control device.
Required properties:
- compatible: "brcm,bcm2835-gpio"
- reg: Should contain the physical address of the GPIO module's registes.
- reg: Should contain the physical address of the GPIO module's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:

6
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
View File

@ -24,9 +24,9 @@ Required properties for iomux controller:
Required properties for pin configuration node:
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up on this pin. Please refer to fsl,<soc>-pinctrl.txt for the valid
pins and functions of each SoC.
pin working on a specific function, which consists of a tuple of
<mux_reg conf_reg input_reg mux_val input_val>. CONFIG is the pad setting
value like pull-up on this pin.
Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.

955
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
View File

@ -29,956 +29,5 @@ PAD_CTL_DSE_MAX (2 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx35:
0 MX35_PAD_CAPTURE__GPT_CAPIN1
1 MX35_PAD_CAPTURE__GPT_CMPOUT2
2 MX35_PAD_CAPTURE__CSPI2_SS1
3 MX35_PAD_CAPTURE__EPIT1_EPITO
4 MX35_PAD_CAPTURE__CCM_CLK32K
5 MX35_PAD_CAPTURE__GPIO1_4
6 MX35_PAD_COMPARE__GPT_CMPOUT1
7 MX35_PAD_COMPARE__GPT_CAPIN2
8 MX35_PAD_COMPARE__GPT_CMPOUT3
9 MX35_PAD_COMPARE__EPIT2_EPITO
10 MX35_PAD_COMPARE__GPIO1_5
11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
14 MX35_PAD_WDOG_RST__GPIO1_6
15 MX35_PAD_GPIO1_0__GPIO1_0
16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
17 MX35_PAD_GPIO1_0__OWIRE_LINE
18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
19 MX35_PAD_GPIO1_1__GPIO1_1
20 MX35_PAD_GPIO1_1__PWM_PWMO
21 MX35_PAD_GPIO1_1__CSPI1_SS2
22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
24 MX35_PAD_GPIO2_0__GPIO2_0
25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
26 MX35_PAD_GPIO3_0__GPIO3_0
27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
29 MX35_PAD_POR_B__CCM_POR_B
30 MX35_PAD_CLKO__CCM_CLKO
31 MX35_PAD_CLKO__GPIO1_8
32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
37 MX35_PAD_VSTBY__CCM_VSTBY
38 MX35_PAD_VSTBY__GPIO1_7
39 MX35_PAD_A0__EMI_EIM_DA_L_0
40 MX35_PAD_A1__EMI_EIM_DA_L_1
41 MX35_PAD_A2__EMI_EIM_DA_L_2
42 MX35_PAD_A3__EMI_EIM_DA_L_3
43 MX35_PAD_A4__EMI_EIM_DA_L_4
44 MX35_PAD_A5__EMI_EIM_DA_L_5
45 MX35_PAD_A6__EMI_EIM_DA_L_6
46 MX35_PAD_A7__EMI_EIM_DA_L_7
47 MX35_PAD_A8__EMI_EIM_DA_H_8
48 MX35_PAD_A9__EMI_EIM_DA_H_9
49 MX35_PAD_A10__EMI_EIM_DA_H_10
50 MX35_PAD_MA10__EMI_MA10
51 MX35_PAD_A11__EMI_EIM_DA_H_11
52 MX35_PAD_A12__EMI_EIM_DA_H_12
53 MX35_PAD_A13__EMI_EIM_DA_H_13
54 MX35_PAD_A14__EMI_EIM_DA_H2_14
55 MX35_PAD_A15__EMI_EIM_DA_H2_15
56 MX35_PAD_A16__EMI_EIM_A_16
57 MX35_PAD_A17__EMI_EIM_A_17
58 MX35_PAD_A18__EMI_EIM_A_18
59 MX35_PAD_A19__EMI_EIM_A_19
60 MX35_PAD_A20__EMI_EIM_A_20
61 MX35_PAD_A21__EMI_EIM_A_21
62 MX35_PAD_A22__EMI_EIM_A_22
63 MX35_PAD_A23__EMI_EIM_A_23
64 MX35_PAD_A24__EMI_EIM_A_24
65 MX35_PAD_A25__EMI_EIM_A_25
66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
68 MX35_PAD_SD0__EMI_DRAM_D_0
69 MX35_PAD_SD1__EMI_DRAM_D_1
70 MX35_PAD_SD2__EMI_DRAM_D_2
71 MX35_PAD_SD3__EMI_DRAM_D_3
72 MX35_PAD_SD4__EMI_DRAM_D_4
73 MX35_PAD_SD5__EMI_DRAM_D_5
74 MX35_PAD_SD6__EMI_DRAM_D_6
75 MX35_PAD_SD7__EMI_DRAM_D_7
76 MX35_PAD_SD8__EMI_DRAM_D_8
77 MX35_PAD_SD9__EMI_DRAM_D_9
78 MX35_PAD_SD10__EMI_DRAM_D_10
79 MX35_PAD_SD11__EMI_DRAM_D_11
80 MX35_PAD_SD12__EMI_DRAM_D_12
81 MX35_PAD_SD13__EMI_DRAM_D_13
82 MX35_PAD_SD14__EMI_DRAM_D_14
83 MX35_PAD_SD15__EMI_DRAM_D_15
84 MX35_PAD_SD16__EMI_DRAM_D_16
85 MX35_PAD_SD17__EMI_DRAM_D_17
86 MX35_PAD_SD18__EMI_DRAM_D_18
87 MX35_PAD_SD19__EMI_DRAM_D_19
88 MX35_PAD_SD20__EMI_DRAM_D_20
89 MX35_PAD_SD21__EMI_DRAM_D_21
90 MX35_PAD_SD22__EMI_DRAM_D_22
91 MX35_PAD_SD23__EMI_DRAM_D_23
92 MX35_PAD_SD24__EMI_DRAM_D_24
93 MX35_PAD_SD25__EMI_DRAM_D_25
94 MX35_PAD_SD26__EMI_DRAM_D_26
95 MX35_PAD_SD27__EMI_DRAM_D_27
96 MX35_PAD_SD28__EMI_DRAM_D_28
97 MX35_PAD_SD29__EMI_DRAM_D_29
98 MX35_PAD_SD30__EMI_DRAM_D_30
99 MX35_PAD_SD31__EMI_DRAM_D_31
100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
104 MX35_PAD_EB0__EMI_EIM_EB0_B
105 MX35_PAD_EB1__EMI_EIM_EB1_B
106 MX35_PAD_OE__EMI_EIM_OE
107 MX35_PAD_CS0__EMI_EIM_CS0
108 MX35_PAD_CS1__EMI_EIM_CS1
109 MX35_PAD_CS1__EMI_NANDF_CE3
110 MX35_PAD_CS2__EMI_EIM_CS2
111 MX35_PAD_CS3__EMI_EIM_CS3
112 MX35_PAD_CS4__EMI_EIM_CS4
113 MX35_PAD_CS4__EMI_DTACK_B
114 MX35_PAD_CS4__EMI_NANDF_CE1
115 MX35_PAD_CS4__GPIO1_20
116 MX35_PAD_CS5__EMI_EIM_CS5
117 MX35_PAD_CS5__CSPI2_SS2
118 MX35_PAD_CS5__CSPI1_SS2
119 MX35_PAD_CS5__EMI_NANDF_CE2
120 MX35_PAD_CS5__GPIO1_21
121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
122 MX35_PAD_NF_CE0__GPIO1_22
123 MX35_PAD_ECB__EMI_EIM_ECB
124 MX35_PAD_LBA__EMI_EIM_LBA
125 MX35_PAD_BCLK__EMI_EIM_BCLK
126 MX35_PAD_RW__EMI_EIM_RW
127 MX35_PAD_RAS__EMI_DRAM_RAS
128 MX35_PAD_CAS__EMI_DRAM_CAS
129 MX35_PAD_SDWE__EMI_DRAM_SDWE
130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
140 MX35_PAD_NFWE_B__GPIO2_18
141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
145 MX35_PAD_NFRE_B__GPIO2_19
146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
147 MX35_PAD_NFALE__EMI_NANDF_ALE
148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
149 MX35_PAD_NFALE__IPU_DISPB_CS0
150 MX35_PAD_NFALE__GPIO2_20
151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
152 MX35_PAD_NFCLE__EMI_NANDF_CLE
153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
155 MX35_PAD_NFCLE__GPIO2_21
156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
159 MX35_PAD_NFWP_B__IPU_DISPB_WR
160 MX35_PAD_NFWP_B__GPIO2_22
161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
162 MX35_PAD_NFRB__EMI_NANDF_RB
163 MX35_PAD_NFRB__IPU_DISPB_RD
164 MX35_PAD_NFRB__GPIO2_23
165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
166 MX35_PAD_D15__EMI_EIM_D_15
167 MX35_PAD_D14__EMI_EIM_D_14
168 MX35_PAD_D13__EMI_EIM_D_13
169 MX35_PAD_D12__EMI_EIM_D_12
170 MX35_PAD_D11__EMI_EIM_D_11
171 MX35_PAD_D10__EMI_EIM_D_10
172 MX35_PAD_D9__EMI_EIM_D_9
173 MX35_PAD_D8__EMI_EIM_D_8
174 MX35_PAD_D7__EMI_EIM_D_7
175 MX35_PAD_D6__EMI_EIM_D_6
176 MX35_PAD_D5__EMI_EIM_D_5
177 MX35_PAD_D4__EMI_EIM_D_4
178 MX35_PAD_D3__EMI_EIM_D_3
179 MX35_PAD_D2__EMI_EIM_D_2
180 MX35_PAD_D1__EMI_EIM_D_1
181 MX35_PAD_D0__EMI_EIM_D_0
182 MX35_PAD_CSI_D8__IPU_CSI_D_8
183 MX35_PAD_CSI_D8__KPP_COL_0
184 MX35_PAD_CSI_D8__GPIO1_20
185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
186 MX35_PAD_CSI_D9__IPU_CSI_D_9
187 MX35_PAD_CSI_D9__KPP_COL_1
188 MX35_PAD_CSI_D9__GPIO1_21
189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
190 MX35_PAD_CSI_D10__IPU_CSI_D_10
191 MX35_PAD_CSI_D10__KPP_COL_2
192 MX35_PAD_CSI_D10__GPIO1_22
193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
194 MX35_PAD_CSI_D11__IPU_CSI_D_11
195 MX35_PAD_CSI_D11__KPP_COL_3
196 MX35_PAD_CSI_D11__GPIO1_23
197 MX35_PAD_CSI_D12__IPU_CSI_D_12
198 MX35_PAD_CSI_D12__KPP_ROW_0
199 MX35_PAD_CSI_D12__GPIO1_24
200 MX35_PAD_CSI_D13__IPU_CSI_D_13
201 MX35_PAD_CSI_D13__KPP_ROW_1
202 MX35_PAD_CSI_D13__GPIO1_25
203 MX35_PAD_CSI_D14__IPU_CSI_D_14
204 MX35_PAD_CSI_D14__KPP_ROW_2
205 MX35_PAD_CSI_D14__GPIO1_26
206 MX35_PAD_CSI_D15__IPU_CSI_D_15
207 MX35_PAD_CSI_D15__KPP_ROW_3
208 MX35_PAD_CSI_D15__GPIO1_27
209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
210 MX35_PAD_CSI_MCLK__GPIO1_28
211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
212 MX35_PAD_CSI_VSYNC__GPIO1_29
213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
214 MX35_PAD_CSI_HSYNC__GPIO1_30
215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
216 MX35_PAD_CSI_PIXCLK__GPIO1_31
217 MX35_PAD_I2C1_CLK__I2C1_SCL
218 MX35_PAD_I2C1_CLK__GPIO2_24
219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
220 MX35_PAD_I2C1_DAT__I2C1_SDA
221 MX35_PAD_I2C1_DAT__GPIO2_25
222 MX35_PAD_I2C2_CLK__I2C2_SCL
223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
225 MX35_PAD_I2C2_CLK__GPIO2_26
226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
227 MX35_PAD_I2C2_DAT__I2C2_SDA
228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
230 MX35_PAD_I2C2_DAT__GPIO2_27
231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
233 MX35_PAD_STXD4__GPIO2_28
234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
236 MX35_PAD_SRXD4__GPIO2_29
237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
239 MX35_PAD_SCK4__GPIO2_30
240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
242 MX35_PAD_STXFS4__GPIO2_31
243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
246 MX35_PAD_STXD5__CSPI2_MOSI
247 MX35_PAD_STXD5__GPIO1_0
248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
251 MX35_PAD_SRXD5__CSPI2_MISO
252 MX35_PAD_SRXD5__GPIO1_1
253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
256 MX35_PAD_SCK5__CSPI2_SCLK
257 MX35_PAD_SCK5__GPIO1_2
258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
260 MX35_PAD_STXFS5__CSPI2_RDY
261 MX35_PAD_STXFS5__GPIO1_3
262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
263 MX35_PAD_SCKR__ESAI_SCKR
264 MX35_PAD_SCKR__GPIO1_4
265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
266 MX35_PAD_FSR__ESAI_FSR
267 MX35_PAD_FSR__GPIO1_5
268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
269 MX35_PAD_HCKR__ESAI_HCKR
270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
271 MX35_PAD_HCKR__CSPI2_SS0
272 MX35_PAD_HCKR__IPU_FLASH_STROBE
273 MX35_PAD_HCKR__GPIO1_6
274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
275 MX35_PAD_SCKT__ESAI_SCKT
276 MX35_PAD_SCKT__GPIO1_7
277 MX35_PAD_SCKT__IPU_CSI_D_0
278 MX35_PAD_SCKT__KPP_ROW_2
279 MX35_PAD_FST__ESAI_FST
280 MX35_PAD_FST__GPIO1_8
281 MX35_PAD_FST__IPU_CSI_D_1
282 MX35_PAD_FST__KPP_ROW_3
283 MX35_PAD_HCKT__ESAI_HCKT
284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
285 MX35_PAD_HCKT__GPIO1_9
286 MX35_PAD_HCKT__IPU_CSI_D_2
287 MX35_PAD_HCKT__KPP_COL_3
288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
290 MX35_PAD_TX5_RX0__CSPI2_SS2
291 MX35_PAD_TX5_RX0__CAN2_TXCAN
292 MX35_PAD_TX5_RX0__UART2_DTR
293 MX35_PAD_TX5_RX0__GPIO1_10
294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
297 MX35_PAD_TX4_RX1__CSPI2_SS3
298 MX35_PAD_TX4_RX1__CAN2_RXCAN
299 MX35_PAD_TX4_RX1__UART2_DSR
300 MX35_PAD_TX4_RX1__GPIO1_11
301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
302 MX35_PAD_TX4_RX1__KPP_ROW_0
303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
304 MX35_PAD_TX3_RX2__I2C3_SCL
305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
306 MX35_PAD_TX3_RX2__GPIO1_12
307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
308 MX35_PAD_TX3_RX2__KPP_ROW_1
309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
310 MX35_PAD_TX2_RX3__I2C3_SDA
311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
312 MX35_PAD_TX2_RX3__GPIO1_13
313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
314 MX35_PAD_TX2_RX3__KPP_COL_0
315 MX35_PAD_TX1__ESAI_TX1
316 MX35_PAD_TX1__CCM_PMIC_RDY
317 MX35_PAD_TX1__CSPI1_SS2
318 MX35_PAD_TX1__EMI_NANDF_CE3
319 MX35_PAD_TX1__UART2_RI
320 MX35_PAD_TX1__GPIO1_14
321 MX35_PAD_TX1__IPU_CSI_D_6
322 MX35_PAD_TX1__KPP_COL_1
323 MX35_PAD_TX0__ESAI_TX0
324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
325 MX35_PAD_TX0__CSPI1_SS3
326 MX35_PAD_TX0__EMI_DTACK_B
327 MX35_PAD_TX0__UART2_DCD
328 MX35_PAD_TX0__GPIO1_15
329 MX35_PAD_TX0__IPU_CSI_D_7
330 MX35_PAD_TX0__KPP_COL_2
331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
332 MX35_PAD_CSPI1_MOSI__GPIO1_16
333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
335 MX35_PAD_CSPI1_MISO__GPIO1_17
336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
340 MX35_PAD_CSPI1_SS0__GPIO1_18
341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
343 MX35_PAD_CSPI1_SS1__PWM_PWMO
344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
345 MX35_PAD_CSPI1_SS1__GPIO1_19
346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
349 MX35_PAD_CSPI1_SCLK__GPIO3_4
350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
356 MX35_PAD_RXD1__UART1_RXD_MUX
357 MX35_PAD_RXD1__CSPI2_MOSI
358 MX35_PAD_RXD1__KPP_COL_4
359 MX35_PAD_RXD1__GPIO3_6
360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
361 MX35_PAD_TXD1__UART1_TXD_MUX
362 MX35_PAD_TXD1__CSPI2_MISO
363 MX35_PAD_TXD1__KPP_COL_5
364 MX35_PAD_TXD1__GPIO3_7
365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
366 MX35_PAD_RTS1__UART1_RTS
367 MX35_PAD_RTS1__CSPI2_SCLK
368 MX35_PAD_RTS1__I2C3_SCL
369 MX35_PAD_RTS1__IPU_CSI_D_0
370 MX35_PAD_RTS1__KPP_COL_6
371 MX35_PAD_RTS1__GPIO3_8
372 MX35_PAD_RTS1__EMI_NANDF_CE1
373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
374 MX35_PAD_CTS1__UART1_CTS
375 MX35_PAD_CTS1__CSPI2_RDY
376 MX35_PAD_CTS1__I2C3_SDA
377 MX35_PAD_CTS1__IPU_CSI_D_1
378 MX35_PAD_CTS1__KPP_COL_7
379 MX35_PAD_CTS1__GPIO3_9
380 MX35_PAD_CTS1__EMI_NANDF_CE2
381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
382 MX35_PAD_RXD2__UART2_RXD_MUX
383 MX35_PAD_RXD2__KPP_ROW_4
384 MX35_PAD_RXD2__GPIO3_10
385 MX35_PAD_TXD2__UART2_TXD_MUX
386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
387 MX35_PAD_TXD2__KPP_ROW_5
388 MX35_PAD_TXD2__GPIO3_11
389 MX35_PAD_RTS2__UART2_RTS
390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
391 MX35_PAD_RTS2__CAN2_RXCAN
392 MX35_PAD_RTS2__IPU_CSI_D_2
393 MX35_PAD_RTS2__KPP_ROW_6
394 MX35_PAD_RTS2__GPIO3_12
395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
396 MX35_PAD_RTS2__UART3_RXD_MUX
397 MX35_PAD_CTS2__UART2_CTS
398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
399 MX35_PAD_CTS2__CAN2_TXCAN
400 MX35_PAD_CTS2__IPU_CSI_D_3
401 MX35_PAD_CTS2__KPP_ROW_7
402 MX35_PAD_CTS2__GPIO3_13
403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
404 MX35_PAD_CTS2__UART3_TXD_MUX
405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
406 MX35_PAD_TCK__SJC_TCK
407 MX35_PAD_TMS__SJC_TMS
408 MX35_PAD_TDI__SJC_TDI
409 MX35_PAD_TDO__SJC_TDO
410 MX35_PAD_TRSTB__SJC_TRSTB
411 MX35_PAD_DE_B__SJC_DE_B
412 MX35_PAD_SJC_MOD__SJC_MOD
413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
415 MX35_PAD_USBOTG_PWR__GPIO3_14
416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
418 MX35_PAD_USBOTG_OC__GPIO3_15
419 MX35_PAD_LD0__IPU_DISPB_DAT_0
420 MX35_PAD_LD0__GPIO2_0
421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
422 MX35_PAD_LD1__IPU_DISPB_DAT_1
423 MX35_PAD_LD1__GPIO2_1
424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
425 MX35_PAD_LD2__IPU_DISPB_DAT_2
426 MX35_PAD_LD2__GPIO2_2
427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
428 MX35_PAD_LD3__IPU_DISPB_DAT_3
429 MX35_PAD_LD3__GPIO2_3
430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
431 MX35_PAD_LD4__IPU_DISPB_DAT_4
432 MX35_PAD_LD4__GPIO2_4
433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
434 MX35_PAD_LD5__IPU_DISPB_DAT_5
435 MX35_PAD_LD5__GPIO2_5
436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
437 MX35_PAD_LD6__IPU_DISPB_DAT_6
438 MX35_PAD_LD6__GPIO2_6
439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
440 MX35_PAD_LD7__IPU_DISPB_DAT_7
441 MX35_PAD_LD7__GPIO2_7
442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
443 MX35_PAD_LD8__IPU_DISPB_DAT_8
444 MX35_PAD_LD8__GPIO2_8
445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
446 MX35_PAD_LD9__IPU_DISPB_DAT_9
447 MX35_PAD_LD9__GPIO2_9
448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
449 MX35_PAD_LD10__IPU_DISPB_DAT_10
450 MX35_PAD_LD10__GPIO2_10
451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
452 MX35_PAD_LD11__IPU_DISPB_DAT_11
453 MX35_PAD_LD11__GPIO2_11
454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
456 MX35_PAD_LD12__IPU_DISPB_DAT_12
457 MX35_PAD_LD12__GPIO2_12
458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
460 MX35_PAD_LD13__IPU_DISPB_DAT_13
461 MX35_PAD_LD13__GPIO2_13
462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
464 MX35_PAD_LD14__IPU_DISPB_DAT_14
465 MX35_PAD_LD14__GPIO2_14
466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
468 MX35_PAD_LD15__IPU_DISPB_DAT_15
469 MX35_PAD_LD15__GPIO2_15
470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
472 MX35_PAD_LD16__IPU_DISPB_DAT_16
473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
474 MX35_PAD_LD16__GPIO2_16
475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
477 MX35_PAD_LD17__IPU_DISPB_DAT_17
478 MX35_PAD_LD17__IPU_DISPB_CS2
479 MX35_PAD_LD17__GPIO2_17
480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
482 MX35_PAD_LD18__IPU_DISPB_DAT_18
483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
485 MX35_PAD_LD18__ESDHC3_CMD
486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
487 MX35_PAD_LD18__GPIO3_24
488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
490 MX35_PAD_LD19__IPU_DISPB_DAT_19
491 MX35_PAD_LD19__IPU_DISPB_BCLK
492 MX35_PAD_LD19__IPU_DISPB_CS1
493 MX35_PAD_LD19__ESDHC3_CLK
494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
495 MX35_PAD_LD19__GPIO3_25
496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
498 MX35_PAD_LD20__IPU_DISPB_DAT_20
499 MX35_PAD_LD20__IPU_DISPB_CS0
500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
501 MX35_PAD_LD20__ESDHC3_DAT0
502 MX35_PAD_LD20__GPIO3_26
503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
505 MX35_PAD_LD21__IPU_DISPB_DAT_21
506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
507 MX35_PAD_LD21__IPU_DISPB_SER_RS
508 MX35_PAD_LD21__ESDHC3_DAT1
509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
510 MX35_PAD_LD21__GPIO3_27
511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
513 MX35_PAD_LD22__IPU_DISPB_DAT_22
514 MX35_PAD_LD22__IPU_DISPB_WR
515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
516 MX35_PAD_LD22__ESDHC3_DAT2
517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
518 MX35_PAD_LD22__GPIO3_28
519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
521 MX35_PAD_LD23__IPU_DISPB_DAT_23
522 MX35_PAD_LD23__IPU_DISPB_RD
523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
524 MX35_PAD_LD23__ESDHC3_DAT3
525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
526 MX35_PAD_LD23__GPIO3_29
527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
531 MX35_PAD_D3_HSYNC__GPIO3_30
532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
536 MX35_PAD_D3_FPSHIFT__GPIO3_31
537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
541 MX35_PAD_D3_DRDY__GPIO1_0
542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
545 MX35_PAD_CONTRAST__GPIO1_1
546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
550 MX35_PAD_D3_VSYNC__GPIO1_2
551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
555 MX35_PAD_D3_REV__GPIO1_3
556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
560 MX35_PAD_D3_CLS__GPIO1_4
561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
565 MX35_PAD_D3_SPL__GPIO1_5
566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
568 MX35_PAD_SD1_CMD__ESDHC1_CMD
569 MX35_PAD_SD1_CMD__MSHC_SCLK
570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
572 MX35_PAD_SD1_CMD__GPIO1_6
573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
574 MX35_PAD_SD1_CLK__ESDHC1_CLK
575 MX35_PAD_SD1_CLK__MSHC_BS
576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
578 MX35_PAD_SD1_CLK__GPIO1_7
579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
584 MX35_PAD_SD1_DATA0__GPIO1_8
585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
590 MX35_PAD_SD1_DATA1__GPIO1_9
591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
596 MX35_PAD_SD1_DATA2__GPIO1_10
597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
602 MX35_PAD_SD1_DATA3__GPIO1_11
603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
604 MX35_PAD_SD2_CMD__ESDHC2_CMD
605 MX35_PAD_SD2_CMD__I2C3_SCL
606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
609 MX35_PAD_SD2_CMD__GPIO2_0
610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
612 MX35_PAD_SD2_CLK__ESDHC2_CLK
613 MX35_PAD_SD2_CLK__I2C3_SDA
614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
617 MX35_PAD_SD2_CLK__GPIO2_1
618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
625 MX35_PAD_SD2_DATA0__GPIO2_2
626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
632 MX35_PAD_SD2_DATA1__GPIO2_3
633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
634 MX35_PAD_SD2_DATA2__UART3_RTS
635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
638 MX35_PAD_SD2_DATA2__GPIO2_4
639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
640 MX35_PAD_SD2_DATA3__UART3_CTS
641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
644 MX35_PAD_SD2_DATA3__GPIO2_5
645 MX35_PAD_ATA_CS0__ATA_CS0
646 MX35_PAD_ATA_CS0__CSPI1_SS3
647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
648 MX35_PAD_ATA_CS0__GPIO2_6
649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
651 MX35_PAD_ATA_CS1__ATA_CS1
652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
653 MX35_PAD_ATA_CS1__CSPI2_SS0
654 MX35_PAD_ATA_CS1__GPIO2_7
655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
657 MX35_PAD_ATA_DIOR__ATA_DIOR
658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
661 MX35_PAD_ATA_DIOR__CSPI2_SS1
662 MX35_PAD_ATA_DIOR__GPIO2_8
663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
665 MX35_PAD_ATA_DIOW__ATA_DIOW
666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
670 MX35_PAD_ATA_DIOW__GPIO2_9
671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
673 MX35_PAD_ATA_DMACK__ATA_DMACK
674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
676 MX35_PAD_ATA_DMACK__CSPI2_MISO
677 MX35_PAD_ATA_DMACK__GPIO2_10
678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
685 MX35_PAD_ATA_RESET_B__GPIO2_11
686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
688 MX35_PAD_ATA_IORDY__ATA_IORDY
689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
693 MX35_PAD_ATA_IORDY__GPIO2_12
694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
696 MX35_PAD_ATA_DATA0__ATA_DATA_0
697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
701 MX35_PAD_ATA_DATA0__GPIO2_13
702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
704 MX35_PAD_ATA_DATA1__ATA_DATA_1
705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
709 MX35_PAD_ATA_DATA1__GPIO2_14
710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
712 MX35_PAD_ATA_DATA2__ATA_DATA_2
713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
717 MX35_PAD_ATA_DATA2__GPIO2_15
718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
720 MX35_PAD_ATA_DATA3__ATA_DATA_3
721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
724 MX35_PAD_ATA_DATA3__GPIO2_16
725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
727 MX35_PAD_ATA_DATA4__ATA_DATA_4
728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
730 MX35_PAD_ATA_DATA4__GPIO2_17
731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
733 MX35_PAD_ATA_DATA5__ATA_DATA_5
734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
735 MX35_PAD_ATA_DATA5__GPIO2_18
736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
738 MX35_PAD_ATA_DATA6__ATA_DATA_6
739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
740 MX35_PAD_ATA_DATA6__UART1_DTR
741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
742 MX35_PAD_ATA_DATA6__GPIO2_19
743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
744 MX35_PAD_ATA_DATA7__ATA_DATA_7
745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
746 MX35_PAD_ATA_DATA7__UART1_DSR
747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
748 MX35_PAD_ATA_DATA7__GPIO2_20
749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
750 MX35_PAD_ATA_DATA8__ATA_DATA_8
751 MX35_PAD_ATA_DATA8__UART3_RTS
752 MX35_PAD_ATA_DATA8__UART1_RI
753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
754 MX35_PAD_ATA_DATA8__GPIO2_21
755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
756 MX35_PAD_ATA_DATA9__ATA_DATA_9
757 MX35_PAD_ATA_DATA9__UART3_CTS
758 MX35_PAD_ATA_DATA9__UART1_DCD
759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
760 MX35_PAD_ATA_DATA9__GPIO2_22
761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
762 MX35_PAD_ATA_DATA10__ATA_DATA_10
763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
765 MX35_PAD_ATA_DATA10__GPIO2_23
766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
767 MX35_PAD_ATA_DATA11__ATA_DATA_11
768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
770 MX35_PAD_ATA_DATA11__GPIO2_24
771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
772 MX35_PAD_ATA_DATA12__ATA_DATA_12
773 MX35_PAD_ATA_DATA12__I2C3_SCL
774 MX35_PAD_ATA_DATA12__GPIO2_25
775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
776 MX35_PAD_ATA_DATA13__ATA_DATA_13
777 MX35_PAD_ATA_DATA13__I2C3_SDA
778 MX35_PAD_ATA_DATA13__GPIO2_26
779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
780 MX35_PAD_ATA_DATA14__ATA_DATA_14
781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
782 MX35_PAD_ATA_DATA14__KPP_ROW_0
783 MX35_PAD_ATA_DATA14__GPIO2_27
784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
785 MX35_PAD_ATA_DATA15__ATA_DATA_15
786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
787 MX35_PAD_ATA_DATA15__KPP_ROW_1
788 MX35_PAD_ATA_DATA15__GPIO2_28
789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
793 MX35_PAD_ATA_INTRQ__GPIO2_29
794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
802 MX35_PAD_ATA_DMARQ__KPP_COL_0
803 MX35_PAD_ATA_DMARQ__GPIO2_31
804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
806 MX35_PAD_ATA_DA0__ATA_DA_0
807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
808 MX35_PAD_ATA_DA0__KPP_COL_1
809 MX35_PAD_ATA_DA0__GPIO3_0
810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
812 MX35_PAD_ATA_DA1__ATA_DA_1
813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
814 MX35_PAD_ATA_DA1__KPP_COL_2
815 MX35_PAD_ATA_DA1__GPIO3_1
816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
818 MX35_PAD_ATA_DA2__ATA_DA_2
819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
820 MX35_PAD_ATA_DA2__KPP_COL_3
821 MX35_PAD_ATA_DA2__GPIO3_2
822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
824 MX35_PAD_MLB_CLK__MLB_MLBCLK
825 MX35_PAD_MLB_CLK__GPIO3_3
826 MX35_PAD_MLB_DAT__MLB_MLBDAT
827 MX35_PAD_MLB_DAT__GPIO3_4
828 MX35_PAD_MLB_SIG__MLB_MLBSIG
829 MX35_PAD_MLB_SIG__GPIO3_5
830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
835 MX35_PAD_FEC_TX_CLK__GPIO3_6
836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
843 MX35_PAD_FEC_RX_CLK__GPIO3_7
844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
848 MX35_PAD_FEC_RX_DV__UART3_RTS
849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
851 MX35_PAD_FEC_RX_DV__GPIO3_8
852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
854 MX35_PAD_FEC_COL__FEC_COL
855 MX35_PAD_FEC_COL__ESDHC1_DAT7
856 MX35_PAD_FEC_COL__UART3_CTS
857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
858 MX35_PAD_FEC_COL__CSPI2_RDY
859 MX35_PAD_FEC_COL__GPIO3_9
860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
863 MX35_PAD_FEC_RDATA0__PWM_PWMO
864 MX35_PAD_FEC_RDATA0__UART3_DTR
865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
867 MX35_PAD_FEC_RDATA0__GPIO3_10
868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
872 MX35_PAD_FEC_TDATA0__UART3_DSR
873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
875 MX35_PAD_FEC_TDATA0__GPIO3_11
876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
880 MX35_PAD_FEC_TX_EN__UART3_RI
881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
882 MX35_PAD_FEC_TX_EN__GPIO3_12
883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
885 MX35_PAD_FEC_MDC__FEC_MDC
886 MX35_PAD_FEC_MDC__CAN2_TXCAN
887 MX35_PAD_FEC_MDC__UART3_DCD
888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
889 MX35_PAD_FEC_MDC__GPIO3_13
890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
892 MX35_PAD_FEC_MDIO__FEC_MDIO
893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
895 MX35_PAD_FEC_MDIO__GPIO3_14
896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
902 MX35_PAD_FEC_TX_ERR__GPIO3_15
903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
909 MX35_PAD_FEC_RX_ERR__GPIO3_16
910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
911 MX35_PAD_FEC_CRS__FEC_CRS
912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
914 MX35_PAD_FEC_CRS__KPP_COL_5
915 MX35_PAD_FEC_CRS__GPIO3_17
916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
921 MX35_PAD_FEC_RDATA1__KPP_COL_6
922 MX35_PAD_FEC_RDATA1__GPIO3_18
923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
927 MX35_PAD_FEC_TDATA1__KPP_COL_7
928 MX35_PAD_FEC_TDATA1__GPIO3_19
929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
934 MX35_PAD_FEC_RDATA2__GPIO3_20
935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
939 MX35_PAD_FEC_TDATA2__GPIO3_21
940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
944 MX35_PAD_FEC_RDATA3__GPIO3_22
945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
949 MX35_PAD_FEC_TDATA3__GPIO3_23
950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
Refer to imx35-pinfunc.h in device tree source folder for all available
imx35 PIN_FUNC_ID.

759
Documentation/devicetree/bindings/pinctrl/fsl,imx51-pinctrl.txt
View File

@ -28,760 +28,5 @@ PAD_CTL_DSE_MAX (3 << 1)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
See below for available PIN_FUNC_ID for imx51:
MX51_PAD_EIM_D16__AUD4_RXFS 0
MX51_PAD_EIM_D16__AUD5_TXD 1
MX51_PAD_EIM_D16__EIM_D16 2
MX51_PAD_EIM_D16__GPIO2_0 3
MX51_PAD_EIM_D16__I2C1_SDA 4
MX51_PAD_EIM_D16__UART2_CTS 5
MX51_PAD_EIM_D16__USBH2_DATA0 6
MX51_PAD_EIM_D17__AUD5_RXD 7
MX51_PAD_EIM_D17__EIM_D17 8
MX51_PAD_EIM_D17__GPIO2_1 9
MX51_PAD_EIM_D17__UART2_RXD 10
MX51_PAD_EIM_D17__UART3_CTS 11
MX51_PAD_EIM_D17__USBH2_DATA1 12
MX51_PAD_EIM_D18__AUD5_TXC 13
MX51_PAD_EIM_D18__EIM_D18 14
MX51_PAD_EIM_D18__GPIO2_2 15
MX51_PAD_EIM_D18__UART2_TXD 16
MX51_PAD_EIM_D18__UART3_RTS 17
MX51_PAD_EIM_D18__USBH2_DATA2 18
MX51_PAD_EIM_D19__AUD4_RXC 19
MX51_PAD_EIM_D19__AUD5_TXFS 20
MX51_PAD_EIM_D19__EIM_D19 21
MX51_PAD_EIM_D19__GPIO2_3 22
MX51_PAD_EIM_D19__I2C1_SCL 23
MX51_PAD_EIM_D19__UART2_RTS 24
MX51_PAD_EIM_D19__USBH2_DATA3 25
MX51_PAD_EIM_D20__AUD4_TXD 26
MX51_PAD_EIM_D20__EIM_D20 27
MX51_PAD_EIM_D20__GPIO2_4 28
MX51_PAD_EIM_D20__SRTC_ALARM_DEB 29
MX51_PAD_EIM_D20__USBH2_DATA4 30
MX51_PAD_EIM_D21__AUD4_RXD 31
MX51_PAD_EIM_D21__EIM_D21 32
MX51_PAD_EIM_D21__GPIO2_5 33
MX51_PAD_EIM_D21__SRTC_ALARM_DEB 34
MX51_PAD_EIM_D21__USBH2_DATA5 35
MX51_PAD_EIM_D22__AUD4_TXC 36
MX51_PAD_EIM_D22__EIM_D22 37
MX51_PAD_EIM_D22__GPIO2_6 38
MX51_PAD_EIM_D22__USBH2_DATA6 39
MX51_PAD_EIM_D23__AUD4_TXFS 40
MX51_PAD_EIM_D23__EIM_D23 41
MX51_PAD_EIM_D23__GPIO2_7 42
MX51_PAD_EIM_D23__SPDIF_OUT1 43
MX51_PAD_EIM_D23__USBH2_DATA7 44
MX51_PAD_EIM_D24__AUD6_RXFS 45
MX51_PAD_EIM_D24__EIM_D24 46
MX51_PAD_EIM_D24__GPIO2_8 47
MX51_PAD_EIM_D24__I2C2_SDA 48
MX51_PAD_EIM_D24__UART3_CTS 49
MX51_PAD_EIM_D24__USBOTG_DATA0 50
MX51_PAD_EIM_D25__EIM_D25 51
MX51_PAD_EIM_D25__KEY_COL6 52
MX51_PAD_EIM_D25__UART2_CTS 53
MX51_PAD_EIM_D25__UART3_RXD 54
MX51_PAD_EIM_D25__USBOTG_DATA1 55
MX51_PAD_EIM_D26__EIM_D26 56
MX51_PAD_EIM_D26__KEY_COL7 57
MX51_PAD_EIM_D26__UART2_RTS 58
MX51_PAD_EIM_D26__UART3_TXD 59
MX51_PAD_EIM_D26__USBOTG_DATA2 60
MX51_PAD_EIM_D27__AUD6_RXC 61
MX51_PAD_EIM_D27__EIM_D27 62
MX51_PAD_EIM_D27__GPIO2_9 63
MX51_PAD_EIM_D27__I2C2_SCL 64
MX51_PAD_EIM_D27__UART3_RTS 65
MX51_PAD_EIM_D27__USBOTG_DATA3 66
MX51_PAD_EIM_D28__AUD6_TXD 67
MX51_PAD_EIM_D28__EIM_D28 68
MX51_PAD_EIM_D28__KEY_ROW4 69
MX51_PAD_EIM_D28__USBOTG_DATA4 70
MX51_PAD_EIM_D29__AUD6_RXD 71
MX51_PAD_EIM_D29__EIM_D29 72
MX51_PAD_EIM_D29__KEY_ROW5 73
MX51_PAD_EIM_D29__USBOTG_DATA5 74
MX51_PAD_EIM_D30__AUD6_TXC 75
MX51_PAD_EIM_D30__EIM_D30 76
MX51_PAD_EIM_D30__KEY_ROW6 77
MX51_PAD_EIM_D30__USBOTG_DATA6 78
MX51_PAD_EIM_D31__AUD6_TXFS 79
MX51_PAD_EIM_D31__EIM_D31 80
MX51_PAD_EIM_D31__KEY_ROW7 81
MX51_PAD_EIM_D31__USBOTG_DATA7 82
MX51_PAD_EIM_A16__EIM_A16 83
MX51_PAD_EIM_A16__GPIO2_10 84
MX51_PAD_EIM_A16__OSC_FREQ_SEL0 85
MX51_PAD_EIM_A17__EIM_A17 86
MX51_PAD_EIM_A17__GPIO2_11 87
MX51_PAD_EIM_A17__OSC_FREQ_SEL1 88
MX51_PAD_EIM_A18__BOOT_LPB0 89
MX51_PAD_EIM_A18__EIM_A18 90
MX51_PAD_EIM_A18__GPIO2_12 91
MX51_PAD_EIM_A19__BOOT_LPB1 92
MX51_PAD_EIM_A19__EIM_A19 93
MX51_PAD_EIM_A19__GPIO2_13 94
MX51_PAD_EIM_A20__BOOT_UART_SRC0 95
MX51_PAD_EIM_A20__EIM_A20 96
MX51_PAD_EIM_A20__GPIO2_14 97
MX51_PAD_EIM_A21__BOOT_UART_SRC1 98
MX51_PAD_EIM_A21__EIM_A21 99
MX51_PAD_EIM_A21__GPIO2_15 100
MX51_PAD_EIM_A22__EIM_A22 101
MX51_PAD_EIM_A22__GPIO2_16 102
MX51_PAD_EIM_A23__BOOT_HPN_EN 103
MX51_PAD_EIM_A23__EIM_A23 104
MX51_PAD_EIM_A23__GPIO2_17 105
MX51_PAD_EIM_A24__EIM_A24 106
MX51_PAD_EIM_A24__GPIO2_18 107
MX51_PAD_EIM_A24__USBH2_CLK 108
MX51_PAD_EIM_A25__DISP1_PIN4 109
MX51_PAD_EIM_A25__EIM_A25 110
MX51_PAD_EIM_A25__GPIO2_19 111
MX51_PAD_EIM_A25__USBH2_DIR 112
MX51_PAD_EIM_A26__CSI1_DATA_EN 113
MX51_PAD_EIM_A26__DISP2_EXT_CLK 114
MX51_PAD_EIM_A26__EIM_A26 115
MX51_PAD_EIM_A26__GPIO2_20 116
MX51_PAD_EIM_A26__USBH2_STP 117
MX51_PAD_EIM_A27__CSI2_DATA_EN 118
MX51_PAD_EIM_A27__DISP1_PIN1 119
MX51_PAD_EIM_A27__EIM_A27 120
MX51_PAD_EIM_A27__GPIO2_21 121
MX51_PAD_EIM_A27__USBH2_NXT 122
MX51_PAD_EIM_EB0__EIM_EB0 123
MX51_PAD_EIM_EB1__EIM_EB1 124
MX51_PAD_EIM_EB2__AUD5_RXFS 125
MX51_PAD_EIM_EB2__CSI1_D2 126
MX51_PAD_EIM_EB2__EIM_EB2 127
MX51_PAD_EIM_EB2__FEC_MDIO 128
MX51_PAD_EIM_EB2__GPIO2_22 129
MX51_PAD_EIM_EB2__GPT_CMPOUT1 130
MX51_PAD_EIM_EB3__AUD5_RXC 131
MX51_PAD_EIM_EB3__CSI1_D3 132
MX51_PAD_EIM_EB3__EIM_EB3 133
MX51_PAD_EIM_EB3__FEC_RDATA1 134
MX51_PAD_EIM_EB3__GPIO2_23 135
MX51_PAD_EIM_EB3__GPT_CMPOUT2 136
MX51_PAD_EIM_OE__EIM_OE 137
MX51_PAD_EIM_OE__GPIO2_24 138
MX51_PAD_EIM_CS0__EIM_CS0 139
MX51_PAD_EIM_CS0__GPIO2_25 140
MX51_PAD_EIM_CS1__EIM_CS1 141
MX51_PAD_EIM_CS1__GPIO2_26 142
MX51_PAD_EIM_CS2__AUD5_TXD 143
MX51_PAD_EIM_CS2__CSI1_D4 144
MX51_PAD_EIM_CS2__EIM_CS2 145
MX51_PAD_EIM_CS2__FEC_RDATA2 146
MX51_PAD_EIM_CS2__GPIO2_27 147
MX51_PAD_EIM_CS2__USBOTG_STP 148
MX51_PAD_EIM_CS3__AUD5_RXD 149
MX51_PAD_EIM_CS3__CSI1_D5 150
MX51_PAD_EIM_CS3__EIM_CS3 151
MX51_PAD_EIM_CS3__FEC_RDATA3 152
MX51_PAD_EIM_CS3__GPIO2_28 153
MX51_PAD_EIM_CS3__USBOTG_NXT 154
MX51_PAD_EIM_CS4__AUD5_TXC 155
MX51_PAD_EIM_CS4__CSI1_D6 156
MX51_PAD_EIM_CS4__EIM_CS4 157
MX51_PAD_EIM_CS4__FEC_RX_ER 158
MX51_PAD_EIM_CS4__GPIO2_29 159
MX51_PAD_EIM_CS4__USBOTG_CLK 160
MX51_PAD_EIM_CS5__AUD5_TXFS 161
MX51_PAD_EIM_CS5__CSI1_D7 162
MX51_PAD_EIM_CS5__DISP1_EXT_CLK 163
MX51_PAD_EIM_CS5__EIM_CS5 164
MX51_PAD_EIM_CS5__FEC_CRS 165
MX51_PAD_EIM_CS5__GPIO2_30 166
MX51_PAD_EIM_CS5__USBOTG_DIR 167
MX51_PAD_EIM_DTACK__EIM_DTACK 168
MX51_PAD_EIM_DTACK__GPIO2_31 169
MX51_PAD_EIM_LBA__EIM_LBA 170
MX51_PAD_EIM_LBA__GPIO3_1 171
MX51_PAD_EIM_CRE__EIM_CRE 172
MX51_PAD_EIM_CRE__GPIO3_2 173
MX51_PAD_DRAM_CS1__DRAM_CS1 174
MX51_PAD_NANDF_WE_B__GPIO3_3 175
MX51_PAD_NANDF_WE_B__NANDF_WE_B 176
MX51_PAD_NANDF_WE_B__PATA_DIOW 177
MX51_PAD_NANDF_WE_B__SD3_DATA0 178
MX51_PAD_NANDF_RE_B__GPIO3_4 179
MX51_PAD_NANDF_RE_B__NANDF_RE_B 180
MX51_PAD_NANDF_RE_B__PATA_DIOR 181
MX51_PAD_NANDF_RE_B__SD3_DATA1 182
MX51_PAD_NANDF_ALE__GPIO3_5 183
MX51_PAD_NANDF_ALE__NANDF_ALE 184
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 185
MX51_PAD_NANDF_CLE__GPIO3_6 186
MX51_PAD_NANDF_CLE__NANDF_CLE 187
MX51_PAD_NANDF_CLE__PATA_RESET_B 188
MX51_PAD_NANDF_WP_B__GPIO3_7 189
MX51_PAD_NANDF_WP_B__NANDF_WP_B 190
MX51_PAD_NANDF_WP_B__PATA_DMACK 191
MX51_PAD_NANDF_WP_B__SD3_DATA2 192
MX51_PAD_NANDF_RB0__ECSPI2_SS1 193
MX51_PAD_NANDF_RB0__GPIO3_8 194
MX51_PAD_NANDF_RB0__NANDF_RB0 195
MX51_PAD_NANDF_RB0__PATA_DMARQ 196
MX51_PAD_NANDF_RB0__SD3_DATA3 197
MX51_PAD_NANDF_RB1__CSPI_MOSI 198
MX51_PAD_NANDF_RB1__ECSPI2_RDY 199
MX51_PAD_NANDF_RB1__GPIO3_9 200
MX51_PAD_NANDF_RB1__NANDF_RB1 201
MX51_PAD_NANDF_RB1__PATA_IORDY 202
MX51_PAD_NANDF_RB1__SD4_CMD 203
MX51_PAD_NANDF_RB2__DISP2_WAIT 204
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 205
MX51_PAD_NANDF_RB2__FEC_COL 206
MX51_PAD_NANDF_RB2__GPIO3_10 207
MX51_PAD_NANDF_RB2__NANDF_RB2 208
MX51_PAD_NANDF_RB2__USBH3_H3_DP 209
MX51_PAD_NANDF_RB2__USBH3_NXT 210
MX51_PAD_NANDF_RB3__DISP1_WAIT 211
MX51_PAD_NANDF_RB3__ECSPI2_MISO 212
MX51_PAD_NANDF_RB3__FEC_RX_CLK 213
MX51_PAD_NANDF_RB3__GPIO3_11 214
MX51_PAD_NANDF_RB3__NANDF_RB3 215
MX51_PAD_NANDF_RB3__USBH3_CLK 216
MX51_PAD_NANDF_RB3__USBH3_H3_DM 217
MX51_PAD_GPIO_NAND__GPIO_NAND 218
MX51_PAD_GPIO_NAND__PATA_INTRQ 219
MX51_PAD_NANDF_CS0__GPIO3_16 220
MX51_PAD_NANDF_CS0__NANDF_CS0 221
MX51_PAD_NANDF_CS1__GPIO3_17 222
MX51_PAD_NANDF_CS1__NANDF_CS1 223
MX51_PAD_NANDF_CS2__CSPI_SCLK 224
MX51_PAD_NANDF_CS2__FEC_TX_ER 225
MX51_PAD_NANDF_CS2__GPIO3_18 226
MX51_PAD_NANDF_CS2__NANDF_CS2 227
MX51_PAD_NANDF_CS2__PATA_CS_0 228
MX51_PAD_NANDF_CS2__SD4_CLK 229
MX51_PAD_NANDF_CS2__USBH3_H1_DP 230
MX51_PAD_NANDF_CS3__FEC_MDC 231
MX51_PAD_NANDF_CS3__GPIO3_19 232
MX51_PAD_NANDF_CS3__NANDF_CS3 233
MX51_PAD_NANDF_CS3__PATA_CS_1 234
MX51_PAD_NANDF_CS3__SD4_DAT0 235
MX51_PAD_NANDF_CS3__USBH3_H1_DM 236
MX51_PAD_NANDF_CS4__FEC_TDATA1 237
MX51_PAD_NANDF_CS4__GPIO3_20 238
MX51_PAD_NANDF_CS4__NANDF_CS4 239
MX51_PAD_NANDF_CS4__PATA_DA_0 240
MX51_PAD_NANDF_CS4__SD4_DAT1 241
MX51_PAD_NANDF_CS4__USBH3_STP 242
MX51_PAD_NANDF_CS5__FEC_TDATA2 243
MX51_PAD_NANDF_CS5__GPIO3_21 244
MX51_PAD_NANDF_CS5__NANDF_CS5 245
MX51_PAD_NANDF_CS5__PATA_DA_1 246
MX51_PAD_NANDF_CS5__SD4_DAT2 247
MX51_PAD_NANDF_CS5__USBH3_DIR 248
MX51_PAD_NANDF_CS6__CSPI_SS3 249
MX51_PAD_NANDF_CS6__FEC_TDATA3 250
MX51_PAD_NANDF_CS6__GPIO3_22 251
MX51_PAD_NANDF_CS6__NANDF_CS6 252
MX51_PAD_NANDF_CS6__PATA_DA_2 253
MX51_PAD_NANDF_CS6__SD4_DAT3 254
MX51_PAD_NANDF_CS7__FEC_TX_EN 255
MX51_PAD_NANDF_CS7__GPIO3_23 256
MX51_PAD_NANDF_CS7__NANDF_CS7 257
MX51_PAD_NANDF_CS7__SD3_CLK 258
MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 259
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 260
MX51_PAD_NANDF_RDY_INT__GPIO3_24 261
MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 262
MX51_PAD_NANDF_RDY_INT__SD3_CMD 263
MX51_PAD_NANDF_D15__ECSPI2_MOSI 264
MX51_PAD_NANDF_D15__GPIO3_25 265
MX51_PAD_NANDF_D15__NANDF_D15 266
MX51_PAD_NANDF_D15__PATA_DATA15 267
MX51_PAD_NANDF_D15__SD3_DAT7 268
MX51_PAD_NANDF_D14__ECSPI2_SS3 269
MX51_PAD_NANDF_D14__GPIO3_26 270
MX51_PAD_NANDF_D14__NANDF_D14 271
MX51_PAD_NANDF_D14__PATA_DATA14 272
MX51_PAD_NANDF_D14__SD3_DAT6 273
MX51_PAD_NANDF_D13__ECSPI2_SS2 274
MX51_PAD_NANDF_D13__GPIO3_27 275
MX51_PAD_NANDF_D13__NANDF_D13 276
MX51_PAD_NANDF_D13__PATA_DATA13 277
MX51_PAD_NANDF_D13__SD3_DAT5 278
MX51_PAD_NANDF_D12__ECSPI2_SS1 279
MX51_PAD_NANDF_D12__GPIO3_28 280
MX51_PAD_NANDF_D12__NANDF_D12 281
MX51_PAD_NANDF_D12__PATA_DATA12 282
MX51_PAD_NANDF_D12__SD3_DAT4 283
MX51_PAD_NANDF_D11__FEC_RX_DV 284
MX51_PAD_NANDF_D11__GPIO3_29 285
MX51_PAD_NANDF_D11__NANDF_D11 286
MX51_PAD_NANDF_D11__PATA_DATA11 287
MX51_PAD_NANDF_D11__SD3_DATA3 288
MX51_PAD_NANDF_D10__GPIO3_30 289
MX51_PAD_NANDF_D10__NANDF_D10 290
MX51_PAD_NANDF_D10__PATA_DATA10 291
MX51_PAD_NANDF_D10__SD3_DATA2 292
MX51_PAD_NANDF_D9__FEC_RDATA0 293
MX51_PAD_NANDF_D9__GPIO3_31 294
MX51_PAD_NANDF_D9__NANDF_D9 295
MX51_PAD_NANDF_D9__PATA_DATA9 296
MX51_PAD_NANDF_D9__SD3_DATA1 297
MX51_PAD_NANDF_D8__FEC_TDATA0 298
MX51_PAD_NANDF_D8__GPIO4_0 299
MX51_PAD_NANDF_D8__NANDF_D8 300
MX51_PAD_NANDF_D8__PATA_DATA8 301
MX51_PAD_NANDF_D8__SD3_DATA0 302
MX51_PAD_NANDF_D7__GPIO4_1 303
MX51_PAD_NANDF_D7__NANDF_D7 304
MX51_PAD_NANDF_D7__PATA_DATA7 305
MX51_PAD_NANDF_D7__USBH3_DATA0 306
MX51_PAD_NANDF_D6__GPIO4_2 307
MX51_PAD_NANDF_D6__NANDF_D6 308
MX51_PAD_NANDF_D6__PATA_DATA6 309
MX51_PAD_NANDF_D6__SD4_LCTL 310
MX51_PAD_NANDF_D6__USBH3_DATA1 311
MX51_PAD_NANDF_D5__GPIO4_3 312
MX51_PAD_NANDF_D5__NANDF_D5 313
MX51_PAD_NANDF_D5__PATA_DATA5 314
MX51_PAD_NANDF_D5__SD4_WP 315
MX51_PAD_NANDF_D5__USBH3_DATA2 316
MX51_PAD_NANDF_D4__GPIO4_4 317
MX51_PAD_NANDF_D4__NANDF_D4 318
MX51_PAD_NANDF_D4__PATA_DATA4 319
MX51_PAD_NANDF_D4__SD4_CD 320
MX51_PAD_NANDF_D4__USBH3_DATA3 321
MX51_PAD_NANDF_D3__GPIO4_5 322
MX51_PAD_NANDF_D3__NANDF_D3 323
MX51_PAD_NANDF_D3__PATA_DATA3 324
MX51_PAD_NANDF_D3__SD4_DAT4 325
MX51_PAD_NANDF_D3__USBH3_DATA4 326
MX51_PAD_NANDF_D2__GPIO4_6 327
MX51_PAD_NANDF_D2__NANDF_D2 328
MX51_PAD_NANDF_D2__PATA_DATA2 329
MX51_PAD_NANDF_D2__SD4_DAT5 330
MX51_PAD_NANDF_D2__USBH3_DATA5 331
MX51_PAD_NANDF_D1__GPIO4_7 332
MX51_PAD_NANDF_D1__NANDF_D1 333
MX51_PAD_NANDF_D1__PATA_DATA1 334
MX51_PAD_NANDF_D1__SD4_DAT6 335
MX51_PAD_NANDF_D1__USBH3_DATA6 336
MX51_PAD_NANDF_D0__GPIO4_8 337
MX51_PAD_NANDF_D0__NANDF_D0 338
MX51_PAD_NANDF_D0__PATA_DATA0 339
MX51_PAD_NANDF_D0__SD4_DAT7 340
MX51_PAD_NANDF_D0__USBH3_DATA7 341
MX51_PAD_CSI1_D8__CSI1_D8 342
MX51_PAD_CSI1_D8__GPIO3_12 343
MX51_PAD_CSI1_D9__CSI1_D9 344
MX51_PAD_CSI1_D9__GPIO3_13 345
MX51_PAD_CSI1_D10__CSI1_D10 346
MX51_PAD_CSI1_D11__CSI1_D11 347
MX51_PAD_CSI1_D12__CSI1_D12 348
MX51_PAD_CSI1_D13__CSI1_D13 349
MX51_PAD_CSI1_D14__CSI1_D14 350
MX51_PAD_CSI1_D15__CSI1_D15 351
MX51_PAD_CSI1_D16__CSI1_D16 352
MX51_PAD_CSI1_D17__CSI1_D17 353
MX51_PAD_CSI1_D18__CSI1_D18 354
MX51_PAD_CSI1_D19__CSI1_D19 355
MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 356
MX51_PAD_CSI1_VSYNC__GPIO3_14 357
MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 358
MX51_PAD_CSI1_HSYNC__GPIO3_15 359
MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 360
MX51_PAD_CSI1_MCLK__CSI1_MCLK 361
MX51_PAD_CSI2_D12__CSI2_D12 362
MX51_PAD_CSI2_D12__GPIO4_9 363
MX51_PAD_CSI2_D13__CSI2_D13 364
MX51_PAD_CSI2_D13__GPIO4_10 365
MX51_PAD_CSI2_D14__CSI2_D14 366
MX51_PAD_CSI2_D15__CSI2_D15 367
MX51_PAD_CSI2_D16__CSI2_D16 368
MX51_PAD_CSI2_D17__CSI2_D17 369
MX51_PAD_CSI2_D18__CSI2_D18 370
MX51_PAD_CSI2_D18__GPIO4_11 371
MX51_PAD_CSI2_D19__CSI2_D19 372
MX51_PAD_CSI2_D19__GPIO4_12 373
MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 374
MX51_PAD_CSI2_VSYNC__GPIO4_13 375
MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 376
MX51_PAD_CSI2_HSYNC__GPIO4_14 377
MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 378
MX51_PAD_CSI2_PIXCLK__GPIO4_15 379
MX51_PAD_I2C1_CLK__GPIO4_16 380
MX51_PAD_I2C1_CLK__I2C1_CLK 381
MX51_PAD_I2C1_DAT__GPIO4_17 382
MX51_PAD_I2C1_DAT__I2C1_DAT 383
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 384
MX51_PAD_AUD3_BB_TXD__GPIO4_18 385
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 386
MX51_PAD_AUD3_BB_RXD__GPIO4_19 387
MX51_PAD_AUD3_BB_RXD__UART3_RXD 388
MX51_PAD_AUD3_BB_CK__AUD3_TXC 389
MX51_PAD_AUD3_BB_CK__GPIO4_20 390
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 391
MX51_PAD_AUD3_BB_FS__GPIO4_21 392
MX51_PAD_AUD3_BB_FS__UART3_TXD 393
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 394
MX51_PAD_CSPI1_MOSI__GPIO4_22 395
MX51_PAD_CSPI1_MOSI__I2C1_SDA 396
MX51_PAD_CSPI1_MISO__AUD4_RXD 397
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 398
MX51_PAD_CSPI1_MISO__GPIO4_23 399
MX51_PAD_CSPI1_SS0__AUD4_TXC 400
MX51_PAD_CSPI1_SS0__ECSPI1_SS0 401
MX51_PAD_CSPI1_SS0__GPIO4_24 402
MX51_PAD_CSPI1_SS1__AUD4_TXD 403
MX51_PAD_CSPI1_SS1__ECSPI1_SS1 404
MX51_PAD_CSPI1_SS1__GPIO4_25 405
MX51_PAD_CSPI1_RDY__AUD4_TXFS 406
MX51_PAD_CSPI1_RDY__ECSPI1_RDY 407
MX51_PAD_CSPI1_RDY__GPIO4_26 408
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 409
MX51_PAD_CSPI1_SCLK__GPIO4_27 410
MX51_PAD_CSPI1_SCLK__I2C1_SCL 411
MX51_PAD_UART1_RXD__GPIO4_28 412
MX51_PAD_UART1_RXD__UART1_RXD 413
MX51_PAD_UART1_TXD__GPIO4_29 414
MX51_PAD_UART1_TXD__PWM2_PWMO 415
MX51_PAD_UART1_TXD__UART1_TXD 416
MX51_PAD_UART1_RTS__GPIO4_30 417
MX51_PAD_UART1_RTS__UART1_RTS 418
MX51_PAD_UART1_CTS__GPIO4_31 419
MX51_PAD_UART1_CTS__UART1_CTS 420
MX51_PAD_UART2_RXD__FIRI_TXD 421
MX51_PAD_UART2_RXD__GPIO1_20 422
MX51_PAD_UART2_RXD__UART2_RXD 423
MX51_PAD_UART2_TXD__FIRI_RXD 424
MX51_PAD_UART2_TXD__GPIO1_21 425
MX51_PAD_UART2_TXD__UART2_TXD 426
MX51_PAD_UART3_RXD__CSI1_D0 427
MX51_PAD_UART3_RXD__GPIO1_22 428
MX51_PAD_UART3_RXD__UART1_DTR 429
MX51_PAD_UART3_RXD__UART3_RXD 430
MX51_PAD_UART3_TXD__CSI1_D1 431
MX51_PAD_UART3_TXD__GPIO1_23 432
MX51_PAD_UART3_TXD__UART1_DSR 433
MX51_PAD_UART3_TXD__UART3_TXD 434
MX51_PAD_OWIRE_LINE__GPIO1_24 435
MX51_PAD_OWIRE_LINE__OWIRE_LINE 436
MX51_PAD_OWIRE_LINE__SPDIF_OUT 437
MX51_PAD_KEY_ROW0__KEY_ROW0 438
MX51_PAD_KEY_ROW1__KEY_ROW1 439
MX51_PAD_KEY_ROW2__KEY_ROW2 440
MX51_PAD_KEY_ROW3__KEY_ROW3 441
MX51_PAD_KEY_COL0__KEY_COL0 442
MX51_PAD_KEY_COL0__PLL1_BYP 443
MX51_PAD_KEY_COL1__KEY_COL1 444
MX51_PAD_KEY_COL1__PLL2_BYP 445
MX51_PAD_KEY_COL2__KEY_COL2 446
MX51_PAD_KEY_COL2__PLL3_BYP 447
MX51_PAD_KEY_COL3__KEY_COL3 448
MX51_PAD_KEY_COL4__I2C2_SCL 449
MX51_PAD_KEY_COL4__KEY_COL4 450
MX51_PAD_KEY_COL4__SPDIF_OUT1 451
MX51_PAD_KEY_COL4__UART1_RI 452
MX51_PAD_KEY_COL4__UART3_RTS 453
MX51_PAD_KEY_COL5__I2C2_SDA 454
MX51_PAD_KEY_COL5__KEY_COL5 455
MX51_PAD_KEY_COL5__UART1_DCD 456
MX51_PAD_KEY_COL5__UART3_CTS 457
MX51_PAD_USBH1_CLK__CSPI_SCLK 458
MX51_PAD_USBH1_CLK__GPIO1_25 459
MX51_PAD_USBH1_CLK__I2C2_SCL 460
MX51_PAD_USBH1_CLK__USBH1_CLK 461
MX51_PAD_USBH1_DIR__CSPI_MOSI 462
MX51_PAD_USBH1_DIR__GPIO1_26 463
MX51_PAD_USBH1_DIR__I2C2_SDA 464
MX51_PAD_USBH1_DIR__USBH1_DIR 465
MX51_PAD_USBH1_STP__CSPI_RDY 466
MX51_PAD_USBH1_STP__GPIO1_27 467
MX51_PAD_USBH1_STP__UART3_RXD 468
MX51_PAD_USBH1_STP__USBH1_STP 469
MX51_PAD_USBH1_NXT__CSPI_MISO 470
MX51_PAD_USBH1_NXT__GPIO1_28 471
MX51_PAD_USBH1_NXT__UART3_TXD 472
MX51_PAD_USBH1_NXT__USBH1_NXT 473
MX51_PAD_USBH1_DATA0__GPIO1_11 474
MX51_PAD_USBH1_DATA0__UART2_CTS 475
MX51_PAD_USBH1_DATA0__USBH1_DATA0 476
MX51_PAD_USBH1_DATA1__GPIO1_12 477
MX51_PAD_USBH1_DATA1__UART2_RXD 478
MX51_PAD_USBH1_DATA1__USBH1_DATA1 479
MX51_PAD_USBH1_DATA2__GPIO1_13 480
MX51_PAD_USBH1_DATA2__UART2_TXD 481
MX51_PAD_USBH1_DATA2__USBH1_DATA2 482
MX51_PAD_USBH1_DATA3__GPIO1_14 483
MX51_PAD_USBH1_DATA3__UART2_RTS 484
MX51_PAD_USBH1_DATA3__USBH1_DATA3 485
MX51_PAD_USBH1_DATA4__CSPI_SS0 486
MX51_PAD_USBH1_DATA4__GPIO1_15 487
MX51_PAD_USBH1_DATA4__USBH1_DATA4 488
MX51_PAD_USBH1_DATA5__CSPI_SS1 489
MX51_PAD_USBH1_DATA5__GPIO1_16 490
MX51_PAD_USBH1_DATA5__USBH1_DATA5 491
MX51_PAD_USBH1_DATA6__CSPI_SS3 492
MX51_PAD_USBH1_DATA6__GPIO1_17 493
MX51_PAD_USBH1_DATA6__USBH1_DATA6 494
MX51_PAD_USBH1_DATA7__ECSPI1_SS3 495
MX51_PAD_USBH1_DATA7__ECSPI2_SS3 496
MX51_PAD_USBH1_DATA7__GPIO1_18 497
MX51_PAD_USBH1_DATA7__USBH1_DATA7 498
MX51_PAD_DI1_PIN11__DI1_PIN11 499
MX51_PAD_DI1_PIN11__ECSPI1_SS2 500
MX51_PAD_DI1_PIN11__GPIO3_0 501
MX51_PAD_DI1_PIN12__DI1_PIN12 502
MX51_PAD_DI1_PIN12__GPIO3_1 503
MX51_PAD_DI1_PIN13__DI1_PIN13 504
MX51_PAD_DI1_PIN13__GPIO3_2 505
MX51_PAD_DI1_D0_CS__DI1_D0_CS 506
MX51_PAD_DI1_D0_CS__GPIO3_3 507
MX51_PAD_DI1_D1_CS__DI1_D1_CS 508
MX51_PAD_DI1_D1_CS__DISP1_PIN14 509
MX51_PAD_DI1_D1_CS__DISP1_PIN5 510
MX51_PAD_DI1_D1_CS__GPIO3_4 511
MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 512
MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 513
MX51_PAD_DISPB2_SER_DIN__GPIO3_5 514
MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 515
MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 516
MX51_PAD_DISPB2_SER_DIO__GPIO3_6 517
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 518
MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 519
MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 520
MX51_PAD_DISPB2_SER_CLK__GPIO3_7 521
MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK 522
MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 523
MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 524
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 525
MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 526
MX51_PAD_DISPB2_SER_RS__GPIO3_8 527
MX51_PAD_DISP1_DAT0__DISP1_DAT0 528
MX51_PAD_DISP1_DAT1__DISP1_DAT1 529
MX51_PAD_DISP1_DAT2__DISP1_DAT2 530
MX51_PAD_DISP1_DAT3__DISP1_DAT3 531
MX51_PAD_DISP1_DAT4__DISP1_DAT4 532
MX51_PAD_DISP1_DAT5__DISP1_DAT5 533
MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 534
MX51_PAD_DISP1_DAT6__DISP1_DAT6 535
MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 536
MX51_PAD_DISP1_DAT7__DISP1_DAT7 537
MX51_PAD_DISP1_DAT8__BOOT_SRC0 538
MX51_PAD_DISP1_DAT8__DISP1_DAT8 539
MX51_PAD_DISP1_DAT9__BOOT_SRC1 540
MX51_PAD_DISP1_DAT9__DISP1_DAT9 541
MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 542
MX51_PAD_DISP1_DAT10__DISP1_DAT10 543
MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 544
MX51_PAD_DISP1_DAT11__DISP1_DAT11 545
MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 546
MX51_PAD_DISP1_DAT12__DISP1_DAT12 547
MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 548
MX51_PAD_DISP1_DAT13__DISP1_DAT13 549
MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 550
MX51_PAD_DISP1_DAT14__DISP1_DAT14 551
MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 552
MX51_PAD_DISP1_DAT15__DISP1_DAT15 553
MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 554
MX51_PAD_DISP1_DAT16__DISP1_DAT16 555
MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 556
MX51_PAD_DISP1_DAT17__DISP1_DAT17 557
MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 558
MX51_PAD_DISP1_DAT18__DISP1_DAT18 559
MX51_PAD_DISP1_DAT18__DISP2_PIN11 560
MX51_PAD_DISP1_DAT18__DISP2_PIN5 561
MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 562
MX51_PAD_DISP1_DAT19__DISP1_DAT19 563
MX51_PAD_DISP1_DAT19__DISP2_PIN12 564
MX51_PAD_DISP1_DAT19__DISP2_PIN6 565
MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 566
MX51_PAD_DISP1_DAT20__DISP1_DAT20 567
MX51_PAD_DISP1_DAT20__DISP2_PIN13 568
MX51_PAD_DISP1_DAT20__DISP2_PIN7 569
MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 570
MX51_PAD_DISP1_DAT21__DISP1_DAT21 571
MX51_PAD_DISP1_DAT21__DISP2_PIN14 572
MX51_PAD_DISP1_DAT21__DISP2_PIN8 573
MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 574
MX51_PAD_DISP1_DAT22__DISP1_DAT22 575
MX51_PAD_DISP1_DAT22__DISP2_D0_CS 576
MX51_PAD_DISP1_DAT22__DISP2_DAT16 577
MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 578
MX51_PAD_DISP1_DAT23__DISP1_DAT23 579
MX51_PAD_DISP1_DAT23__DISP2_D1_CS 580
MX51_PAD_DISP1_DAT23__DISP2_DAT17 581
MX51_PAD_DISP1_DAT23__DISP2_SER_CS 582
MX51_PAD_DI1_PIN3__DI1_PIN3 583
MX51_PAD_DI1_PIN2__DI1_PIN2 584
MX51_PAD_DI_GP2__DISP1_SER_CLK 585
MX51_PAD_DI_GP2__DISP2_WAIT 586
MX51_PAD_DI_GP3__CSI1_DATA_EN 587
MX51_PAD_DI_GP3__DISP1_SER_DIO 588
MX51_PAD_DI_GP3__FEC_TX_ER 589
MX51_PAD_DI2_PIN4__CSI2_DATA_EN 590
MX51_PAD_DI2_PIN4__DI2_PIN4 591
MX51_PAD_DI2_PIN4__FEC_CRS 592
MX51_PAD_DI2_PIN2__DI2_PIN2 593
MX51_PAD_DI2_PIN2__FEC_MDC 594
MX51_PAD_DI2_PIN3__DI2_PIN3 595
MX51_PAD_DI2_PIN3__FEC_MDIO 596
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 597
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 598
MX51_PAD_DI_GP4__DI2_PIN15 599
MX51_PAD_DI_GP4__DISP1_SER_DIN 600
MX51_PAD_DI_GP4__DISP2_PIN1 601
MX51_PAD_DI_GP4__FEC_RDATA2 602
MX51_PAD_DISP2_DAT0__DISP2_DAT0 603
MX51_PAD_DISP2_DAT0__FEC_RDATA3 604
MX51_PAD_DISP2_DAT0__KEY_COL6 605
MX51_PAD_DISP2_DAT0__UART3_RXD 606
MX51_PAD_DISP2_DAT0__USBH3_CLK 607
MX51_PAD_DISP2_DAT1__DISP2_DAT1 608
MX51_PAD_DISP2_DAT1__FEC_RX_ER 609
MX51_PAD_DISP2_DAT1__KEY_COL7 610
MX51_PAD_DISP2_DAT1__UART3_TXD 611
MX51_PAD_DISP2_DAT1__USBH3_DIR 612
MX51_PAD_DISP2_DAT2__DISP2_DAT2 613
MX51_PAD_DISP2_DAT3__DISP2_DAT3 614
MX51_PAD_DISP2_DAT4__DISP2_DAT4 615
MX51_PAD_DISP2_DAT5__DISP2_DAT5 616
MX51_PAD_DISP2_DAT6__DISP2_DAT6 617
MX51_PAD_DISP2_DAT6__FEC_TDATA1 618
MX51_PAD_DISP2_DAT6__GPIO1_19 619
MX51_PAD_DISP2_DAT6__KEY_ROW4 620
MX51_PAD_DISP2_DAT6__USBH3_STP 621
MX51_PAD_DISP2_DAT7__DISP2_DAT7 622
MX51_PAD_DISP2_DAT7__FEC_TDATA2 623
MX51_PAD_DISP2_DAT7__GPIO1_29 624
MX51_PAD_DISP2_DAT7__KEY_ROW5 625
MX51_PAD_DISP2_DAT7__USBH3_NXT 626
MX51_PAD_DISP2_DAT8__DISP2_DAT8 627
MX51_PAD_DISP2_DAT8__FEC_TDATA3 628
MX51_PAD_DISP2_DAT8__GPIO1_30 629
MX51_PAD_DISP2_DAT8__KEY_ROW6 630
MX51_PAD_DISP2_DAT8__USBH3_DATA0 631
MX51_PAD_DISP2_DAT9__AUD6_RXC 632
MX51_PAD_DISP2_DAT9__DISP2_DAT9 633
MX51_PAD_DISP2_DAT9__FEC_TX_EN 634
MX51_PAD_DISP2_DAT9__GPIO1_31 635
MX51_PAD_DISP2_DAT9__USBH3_DATA1 636
MX51_PAD_DISP2_DAT10__DISP2_DAT10 637
MX51_PAD_DISP2_DAT10__DISP2_SER_CS 638
MX51_PAD_DISP2_DAT10__FEC_COL 639
MX51_PAD_DISP2_DAT10__KEY_ROW7 640
MX51_PAD_DISP2_DAT10__USBH3_DATA2 641
MX51_PAD_DISP2_DAT11__AUD6_TXD 642
MX51_PAD_DISP2_DAT11__DISP2_DAT11 643
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 644
MX51_PAD_DISP2_DAT11__GPIO1_10 645
MX51_PAD_DISP2_DAT11__USBH3_DATA3 646
MX51_PAD_DISP2_DAT12__AUD6_RXD 647
MX51_PAD_DISP2_DAT12__DISP2_DAT12 648
MX51_PAD_DISP2_DAT12__FEC_RX_DV 649
MX51_PAD_DISP2_DAT12__USBH3_DATA4 650
MX51_PAD_DISP2_DAT13__AUD6_TXC 651
MX51_PAD_DISP2_DAT13__DISP2_DAT13 652
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 653
MX51_PAD_DISP2_DAT13__USBH3_DATA5 654
MX51_PAD_DISP2_DAT14__AUD6_TXFS 655
MX51_PAD_DISP2_DAT14__DISP2_DAT14 656
MX51_PAD_DISP2_DAT14__FEC_RDATA0 657
MX51_PAD_DISP2_DAT14__USBH3_DATA6 658
MX51_PAD_DISP2_DAT15__AUD6_RXFS 659
MX51_PAD_DISP2_DAT15__DISP1_SER_CS 660
MX51_PAD_DISP2_DAT15__DISP2_DAT15 661
MX51_PAD_DISP2_DAT15__FEC_TDATA0 662
MX51_PAD_DISP2_DAT15__USBH3_DATA7 663
MX51_PAD_SD1_CMD__AUD5_RXFS 664
MX51_PAD_SD1_CMD__CSPI_MOSI 665
MX51_PAD_SD1_CMD__SD1_CMD 666
MX51_PAD_SD1_CLK__AUD5_RXC 667
MX51_PAD_SD1_CLK__CSPI_SCLK 668
MX51_PAD_SD1_CLK__SD1_CLK 669
MX51_PAD_SD1_DATA0__AUD5_TXD 670
MX51_PAD_SD1_DATA0__CSPI_MISO 671
MX51_PAD_SD1_DATA0__SD1_DATA0 672
MX51_PAD_EIM_DA0__EIM_DA0 673
MX51_PAD_EIM_DA1__EIM_DA1 674
MX51_PAD_EIM_DA2__EIM_DA2 675
MX51_PAD_EIM_DA3__EIM_DA3 676
MX51_PAD_SD1_DATA1__AUD5_RXD 677
MX51_PAD_SD1_DATA1__SD1_DATA1 678
MX51_PAD_EIM_DA4__EIM_DA4 679
MX51_PAD_EIM_DA5__EIM_DA5 680
MX51_PAD_EIM_DA6__EIM_DA6 681
MX51_PAD_EIM_DA7__EIM_DA7 682
MX51_PAD_SD1_DATA2__AUD5_TXC 683
MX51_PAD_SD1_DATA2__SD1_DATA2 684
MX51_PAD_EIM_DA10__EIM_DA10 685
MX51_PAD_EIM_DA11__EIM_DA11 686
MX51_PAD_EIM_DA8__EIM_DA8 687
MX51_PAD_EIM_DA9__EIM_DA9 688
MX51_PAD_SD1_DATA3__AUD5_TXFS 689
MX51_PAD_SD1_DATA3__CSPI_SS1 690
MX51_PAD_SD1_DATA3__SD1_DATA3 691
MX51_PAD_GPIO1_0__CSPI_SS2 692
MX51_PAD_GPIO1_0__GPIO1_0 693
MX51_PAD_GPIO1_0__SD1_CD 694
MX51_PAD_GPIO1_1__CSPI_MISO 695
MX51_PAD_GPIO1_1__GPIO1_1 696
MX51_PAD_GPIO1_1__SD1_WP 697
MX51_PAD_EIM_DA12__EIM_DA12 698
MX51_PAD_EIM_DA13__EIM_DA13 699
MX51_PAD_EIM_DA14__EIM_DA14 700
MX51_PAD_EIM_DA15__EIM_DA15 701
MX51_PAD_SD2_CMD__CSPI_MOSI 702
MX51_PAD_SD2_CMD__I2C1_SCL 703
MX51_PAD_SD2_CMD__SD2_CMD 704
MX51_PAD_SD2_CLK__CSPI_SCLK 705
MX51_PAD_SD2_CLK__I2C1_SDA 706
MX51_PAD_SD2_CLK__SD2_CLK 707
MX51_PAD_SD2_DATA0__CSPI_MISO 708
MX51_PAD_SD2_DATA0__SD1_DAT4 709
MX51_PAD_SD2_DATA0__SD2_DATA0 710
MX51_PAD_SD2_DATA1__SD1_DAT5 711
MX51_PAD_SD2_DATA1__SD2_DATA1 712
MX51_PAD_SD2_DATA1__USBH3_H2_DP 713
MX51_PAD_SD2_DATA2__SD1_DAT6 714
MX51_PAD_SD2_DATA2__SD2_DATA2 715
MX51_PAD_SD2_DATA2__USBH3_H2_DM 716
MX51_PAD_SD2_DATA3__CSPI_SS2 717
MX51_PAD_SD2_DATA3__SD1_DAT7 718
MX51_PAD_SD2_DATA3__SD2_DATA3 719
MX51_PAD_GPIO1_2__CCM_OUT_2 720
MX51_PAD_GPIO1_2__GPIO1_2 721
MX51_PAD_GPIO1_2__I2C2_SCL 722
MX51_PAD_GPIO1_2__PLL1_BYP 723
MX51_PAD_GPIO1_2__PWM1_PWMO 724
MX51_PAD_GPIO1_3__GPIO1_3 725
MX51_PAD_GPIO1_3__I2C2_SDA 726
MX51_PAD_GPIO1_3__PLL2_BYP 727
MX51_PAD_GPIO1_3__PWM2_PWMO 728
MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 729
MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 730
MX51_PAD_GPIO1_4__DISP2_EXT_CLK 731
MX51_PAD_GPIO1_4__EIM_RDY 732
MX51_PAD_GPIO1_4__GPIO1_4 733
MX51_PAD_GPIO1_4__WDOG1_WDOG_B 734
MX51_PAD_GPIO1_5__CSI2_MCLK 735
MX51_PAD_GPIO1_5__DISP2_PIN16 736
MX51_PAD_GPIO1_5__GPIO1_5 737
MX51_PAD_GPIO1_5__WDOG2_WDOG_B 738
MX51_PAD_GPIO1_6__DISP2_PIN17 739
MX51_PAD_GPIO1_6__GPIO1_6 740
MX51_PAD_GPIO1_6__REF_EN_B 741
MX51_PAD_GPIO1_7__CCM_OUT_0 742
MX51_PAD_GPIO1_7__GPIO1_7 743
MX51_PAD_GPIO1_7__SD2_WP 744
MX51_PAD_GPIO1_7__SPDIF_OUT1 745
MX51_PAD_GPIO1_8__CSI2_DATA_EN 746
MX51_PAD_GPIO1_8__GPIO1_8 747
MX51_PAD_GPIO1_8__SD2_CD 748
MX51_PAD_GPIO1_8__USBH3_PWR 749
MX51_PAD_GPIO1_9__CCM_OUT_1 750
MX51_PAD_GPIO1_9__DISP2_D1_CS 751
MX51_PAD_GPIO1_9__DISP2_SER_CS 752
MX51_PAD_GPIO1_9__GPIO1_9 753
MX51_PAD_GPIO1_9__SD2_LCTL 754
MX51_PAD_GPIO1_9__USBH3_OC 755
Refer to imx51-pinfunc.h in device tree source folder for all available
imx51 PIN_FUNC_ID.

1174
Documentation/devicetree/bindings/pinctrl/fsl,imx53-pinctrl.txt
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38
Documentation/devicetree/bindings/pinctrl/fsl,imx6dl-pinctrl.txt 100644
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@ -0,0 +1,38 @@
* Freescale IMX6 DualLite/Solo IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6dl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx6dl datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6dl-pinfunc.h in device tree source folder for all available
imx6dl PIN_FUNC_ID.

1596
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39
Documentation/devicetree/bindings/pinctrl/fsl,imx6sl-pinctrl.txt 100644
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@ -0,0 +1,39 @@
* Freescale IMX6 SoloLite IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,imx6sl-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
pin working on a specific function, CONFIG is the pad setting value like
pull-up for this pin. Please refer to imx6sl datasheet for the valid pad
config settings.
CONFIG bits definition:
PAD_CTL_LVE (1 << 22)
PAD_CTL_HYS (1 << 16)
PAD_CTL_PUS_100K_DOWN (0 << 14)
PAD_CTL_PUS_47K_UP (1 << 14)
PAD_CTL_PUS_100K_UP (2 << 14)
PAD_CTL_PUS_22K_UP (3 << 14)
PAD_CTL_PUE (1 << 13)
PAD_CTL_PKE (1 << 12)
PAD_CTL_ODE (1 << 11)
PAD_CTL_SPEED_LOW (1 << 6)
PAD_CTL_SPEED_MED (2 << 6)
PAD_CTL_SPEED_HIGH (3 << 6)
PAD_CTL_DSE_DISABLE (0 << 3)
PAD_CTL_DSE_240ohm (1 << 3)
PAD_CTL_DSE_120ohm (2 << 3)
PAD_CTL_DSE_80ohm (3 << 3)
PAD_CTL_DSE_60ohm (4 << 3)
PAD_CTL_DSE_48ohm (5 << 3)
PAD_CTL_DSE_40ohm (6 << 3)
PAD_CTL_DSE_34ohm (7 << 3)
PAD_CTL_SRE_FAST (1 << 0)
PAD_CTL_SRE_SLOW (0 << 0)
Refer to imx6sl-pinfunc.h in device tree source folder for all available
imx6sl PIN_FUNC_ID.

109
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
View File

@ -1,7 +1,9 @@
One-register-per-pin type device tree based pinctrl driver
Required properties:
- compatible : "pinctrl-single"
- compatible : "pinctrl-single" or "pinconf-single".
"pinctrl-single" means that pinconf isn't supported.
"pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
@ -14,9 +16,61 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
current and drive strength mask.
/* drive strength current, mask */
pinctrl-single,power-source = <0x30 0xf0>;
- pinctrl-single,bias-pullup : array of value that are used to configure the
input bias pullup in the pinmux register.
/* input, enabled pullup bits, disabled pullup bits, mask */
pinctrl-single,bias-pullup = <0 1 0 1>;
- pinctrl-single,bias-pulldown : array of value that are used to configure the
input bias pulldown in the pinmux register.
/* input, enabled pulldown bits, disabled pulldown bits, mask */
pinctrl-single,bias-pulldown = <2 2 0 2>;
* Two bits to control input bias pullup and pulldown: User should use
pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
pullup, and the other one bit means pulldown.
* Three bits to control input bias enable, pullup and pulldown. User should
use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
enable bit should be included in pullup or pulldown bits.
* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
pinctrl-single,bias-disable. Because pinctrl single driver could implement
it by calling pulldown, pullup disabled.
- pinctrl-single,input-schmitt : array of value that are used to configure
input schmitt in the pinmux register. In some silicons, there're two input
schmitt value (rising-edge & falling-edge) in the pinmux register.
/* input schmitt value, mask */
pinctrl-single,input-schmitt = <0x30 0x70>;
- pinctrl-single,input-schmitt-enable : array of value that are used to
configure input schmitt enable or disable in the pinmux register.
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
The number of parameters is depend on #pinctrl-single,gpio-range-cells
property.
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.
Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
pinctrl-single,gpio-range property.
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
Example:
/* SoC common file */
@ -58,7 +126,7 @@ pmx_core: pinmux@4a100040 {
/* second controller instance for pins in wkup domain */
pmx_wkup: pinmux@4a31e040 {
compatible = "pinctrl-single;
compatible = "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
pinctrl-single,function-mask = <0x5F>;
};
/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
compatible = "pinconf-single";
reg = <0xd401e000 0x0330>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* sparse GPIO range could be supported */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
/* board specific .dts file */
&pmx_core {
@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 2>;
pinctrl-single,bias-pullup = <0 1 1>;
};
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;

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