[ARM] nommu: avoid selecting TLB and CPU specific copy code
Since uclinux doesn't make use of the TLB, including the TLB maintainence and CPU-optimised copypage functions does not make sense. Remove them. (This is part of one of Hyok's patches.) Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -15,8 +15,8 @@ config CPU_ARM610
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_COPY_V3
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select CPU_TLB_V3
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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help
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The ARM610 is the successor to the ARM3 processor
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and was produced by VLSI Technology Inc.
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@ -31,8 +31,8 @@ config CPU_ARM710
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select CPU_32v3
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select CPU_CACHE_V3
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select CPU_CACHE_VIVT
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select CPU_COPY_V3
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select CPU_TLB_V3
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select CPU_COPY_V3 if MMU
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select CPU_TLB_V3 if MMU
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help
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A 32-bit RISC microprocessor based on the ARM7 processor core
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designed by Advanced RISC Machines Ltd. The ARM710 is the
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@ -50,8 +50,8 @@ config CPU_ARM720T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V4
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WT
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select CPU_TLB_V4WT
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select CPU_COPY_V4WT if MMU
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select CPU_TLB_V4WT if MMU
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help
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A 32-bit RISC processor with 8kByte Cache, Write Buffer and
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MMU built around an ARM7TDMI core.
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@ -68,8 +68,8 @@ config CPU_ARM920T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM920T is licensed to be produced by numerous vendors,
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and is used in the Maverick EP9312 and the Samsung S3C2410.
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@ -89,8 +89,8 @@ config CPU_ARM922T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM922T is a version of the ARM920T, but with smaller
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instruction and data caches. It is used in Altera's
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@ -108,8 +108,8 @@ config CPU_ARM925T
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM925T is a mix between the ARM920T and ARM926T, but with
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different instruction and data caches. It is used in TI's OMAP
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@ -126,8 +126,8 @@ config CPU_ARM926T
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select CPU_32v5
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select CPU_ABRT_EV5TJ
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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This is a variant of the ARM920. It has slightly different
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instruction sequences for cache and TLB operations. Curiously,
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@ -144,8 +144,8 @@ config CPU_ARM1020
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1020 is the 32K cached version of the ARM10 processor,
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with an addition of a floating-point unit.
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@ -161,8 +161,8 @@ config CPU_ARM1020E
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select CPU_ABRT_EV4T
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select CPU_CACHE_V4WT
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WBI if MMU
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depends on n
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# ARM1022E
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@ -172,8 +172,8 @@ config CPU_ARM1022
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select CPU_32v5
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select CPU_ABRT_EV4T
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB # can probably do better
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1022E is an implementation of the ARMv5TE architecture
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based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
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@ -189,8 +189,8 @@ config CPU_ARM1026
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select CPU_32v5
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select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB # can probably do better
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select CPU_TLB_V4WBI
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select CPU_COPY_V4WB if MMU # can probably do better
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select CPU_TLB_V4WBI if MMU
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help
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The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
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based upon the ARM10 integer core.
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@ -207,8 +207,8 @@ config CPU_SA110
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_COPY_V4WB
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select CPU_TLB_V4WB
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select CPU_COPY_V4WB if MMU
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select CPU_TLB_V4WB if MMU
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help
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The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
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is available at five speeds ranging from 100 MHz to 233 MHz.
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@ -227,7 +227,7 @@ config CPU_SA1100
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select CPU_ABRT_EV4
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select CPU_CACHE_V4WB
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select CPU_CACHE_VIVT
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select CPU_TLB_V4WB
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select CPU_TLB_V4WB if MMU
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# XScale
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config CPU_XSCALE
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@ -237,7 +237,7 @@ config CPU_XSCALE
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_TLB_V4WBI
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select CPU_TLB_V4WBI if MMU
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# XScale Core Version 3
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config CPU_XSC3
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@ -247,7 +247,7 @@ config CPU_XSC3
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_TLB_V4WBI
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select CPU_TLB_V4WBI if MMU
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select IO_36
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# ARMv6
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@ -258,8 +258,8 @@ config CPU_V6
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select CPU_ABRT_EV6
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select CPU_CACHE_V6
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select CPU_CACHE_VIPT
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select CPU_COPY_V6
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select CPU_TLB_V6
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select CPU_COPY_V6 if MMU
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select CPU_TLB_V6 if MMU
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# ARMv6k
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config CPU_32v6K
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@ -334,6 +334,7 @@ config CPU_CACHE_VIVT
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config CPU_CACHE_VIPT
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bool
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if MMU
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# The copy-page model
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config CPU_COPY_V3
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bool
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@ -372,6 +373,8 @@ config CPU_TLB_V4WBI
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config CPU_TLB_V6
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bool
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endif
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#
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# CPU supports 36-bit I/O
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#
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