mtd: nand: atmel: Add ->setup_data_interface() hooks
The NAND controller IP can adapt the NAND controller timings dynamically. Implement the ->setup_data_interface() hook to support this feature. Note that it's not supported on at91rm9200 because this SoC has a completely different SMC block, which is not supported yet. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>hifive-unleashed-5.1
Boris Brezillon
parent
104e442a67
commit
f9ce2eddf1
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@ -308,6 +308,7 @@ config MTD_NAND_CS553X
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config MTD_NAND_ATMEL
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tristate "Support for NAND Flash / SmartMedia on AT91"
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depends on ARCH_AT91
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select MFD_ATMEL_SMC
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help
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Enables support for NAND Flash / Smart Media Card interface
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on Atmel AT91 processors.
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@ -57,6 +57,7 @@
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/atmel-matrix.h>
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#include <linux/mfd/syscon/atmel-smc.h>
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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#include <linux/of_address.h>
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@ -151,6 +152,8 @@ struct atmel_nand_cs {
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void __iomem *virt;
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dma_addr_t dma;
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} io;
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struct atmel_smc_cs_conf smcconf;
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};
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struct atmel_nand {
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@ -196,6 +199,8 @@ struct atmel_nand_controller_ops {
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void (*nand_init)(struct atmel_nand_controller *nc,
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struct atmel_nand *nand);
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int (*ecc_init)(struct atmel_nand *nand);
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int (*setup_data_interface)(struct atmel_nand *nand, int csline,
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const struct nand_data_interface *conf);
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};
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struct atmel_nand_controller_caps {
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@ -1175,6 +1180,295 @@ static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
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return 0;
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}
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static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
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const struct nand_data_interface *conf,
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struct atmel_smc_cs_conf *smcconf)
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{
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u32 ncycles, totalcycles, timeps, mckperiodps;
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struct atmel_nand_controller *nc;
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int ret;
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nc = to_nand_controller(nand->base.controller);
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/* DDR interface not supported. */
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if (conf->type != NAND_SDR_IFACE)
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return -ENOTSUPP;
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/*
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* tRC < 30ns implies EDO mode. This controller does not support this
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* mode.
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*/
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if (conf->timings.sdr.tRC_min < 30)
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return -ENOTSUPP;
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atmel_smc_cs_conf_init(smcconf);
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mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
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mckperiodps *= 1000;
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/*
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* Set write pulse timing. This one is easy to extract:
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*
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* NWE_PULSE = tWP
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
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totalcycles = ncycles;
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ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* The write setup timing depends on the operation done on the NAND.
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* All operations goes through the same data bus, but the operation
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* type depends on the address we are writing to (ALE/CLE address
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* lines).
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* Since we have no way to differentiate the different operations at
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* the SMC level, we must consider the worst case (the biggest setup
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* time among all operation types):
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*
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* NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
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*/
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timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
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conf->timings.sdr.tALS_min);
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timeps = max(timeps, conf->timings.sdr.tDS_min);
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ncycles = DIV_ROUND_UP(timeps, mckperiodps);
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ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
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totalcycles += ncycles;
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ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* As for the write setup timing, the write hold timing depends on the
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* operation done on the NAND:
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*
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* NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
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*/
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timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
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conf->timings.sdr.tALH_min);
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timeps = max3(timeps, conf->timings.sdr.tDH_min,
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conf->timings.sdr.tWH_min);
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ncycles = DIV_ROUND_UP(timeps, mckperiodps);
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totalcycles += ncycles;
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/*
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* The write cycle timing is directly matching tWC, but is also
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* dependent on the other timings on the setup and hold timings we
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* calculated earlier, which gives:
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*
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* NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
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ncycles = max(totalcycles, ncycles);
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ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* We don't want the CS line to be toggled between each byte/word
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* transfer to the NAND. The only way to guarantee that is to have the
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* NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
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*
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* NCS_WR_PULSE = NWE_CYCLE
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*/
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ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* As for the write setup timing, the read hold timing depends on the
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* operation done on the NAND:
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*
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* NRD_HOLD = max(tREH, tRHOH)
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*/
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timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
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ncycles = DIV_ROUND_UP(timeps, mckperiodps);
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totalcycles = ncycles;
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/*
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* TDF = tRHZ - NRD_HOLD
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
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ncycles -= totalcycles;
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/*
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* In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
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* we might end up with a config that does not fit in the TDF field.
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* Just take the max value in this case and hope that the NAND is more
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* tolerant than advertised.
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*/
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if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
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ncycles = ATMEL_SMC_MODE_TDF_MAX;
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else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
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ncycles = ATMEL_SMC_MODE_TDF_MIN;
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smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
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ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
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/*
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* Read pulse timing directly matches tRP:
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*
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* NRD_PULSE = tRP
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
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totalcycles += ncycles;
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ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* The write cycle timing is directly matching tWC, but is also
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* dependent on the setup and hold timings we calculated earlier,
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* which gives:
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*
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* NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
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*
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* NRD_SETUP is always 0.
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*/
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
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ncycles = max(totalcycles, ncycles);
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ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/*
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* We don't want the CS line to be toggled between each byte/word
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* transfer from the NAND. The only way to guarantee that is to have
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* the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
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*
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* NCS_RD_PULSE = NRD_CYCLE
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*/
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ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/* Txxx timings are directly matching tXXX ones. */
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
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ncycles);
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if (ret)
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return ret;
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TADL_SHIFT,
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ncycles);
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if (ret)
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return ret;
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TAR_SHIFT,
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ncycles);
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if (ret)
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return ret;
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TRR_SHIFT,
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ncycles);
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if (ret)
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return ret;
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ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
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ret = atmel_smc_cs_conf_set_timing(smcconf,
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ATMEL_HSMC_TIMINGS_TWB_SHIFT,
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ncycles);
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if (ret)
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return ret;
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/* Attach the CS line to the NFC logic. */
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smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
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/* Set the appropriate data bus width. */
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if (nand->base.options & NAND_BUSWIDTH_16)
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smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
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/* Operate in NRD/NWE READ/WRITEMODE. */
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smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
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ATMEL_SMC_MODE_WRITEMODE_NWE;
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return 0;
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}
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static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
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int csline,
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const struct nand_data_interface *conf)
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{
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struct atmel_nand_controller *nc;
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struct atmel_smc_cs_conf smcconf;
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struct atmel_nand_cs *cs;
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int ret;
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nc = to_nand_controller(nand->base.controller);
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ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
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if (ret)
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return ret;
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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cs = &nand->cs[csline];
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cs->smcconf = smcconf;
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atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
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return 0;
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}
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static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
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int csline,
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const struct nand_data_interface *conf)
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{
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struct atmel_nand_controller *nc;
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struct atmel_smc_cs_conf smcconf;
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struct atmel_nand_cs *cs;
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int ret;
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nc = to_nand_controller(nand->base.controller);
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ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
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if (ret)
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return ret;
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if (csline == NAND_DATA_IFACE_CHECK_ONLY)
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return 0;
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cs = &nand->cs[csline];
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cs->smcconf = smcconf;
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if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
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cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
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atmel_hsmc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
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return 0;
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}
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static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
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const struct nand_data_interface *conf)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct atmel_nand *nand = to_atmel_nand(chip);
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struct atmel_nand_controller *nc;
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nc = to_nand_controller(nand->base.controller);
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if (csline >= nand->numcs ||
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(csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
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return -EINVAL;
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return nc->caps->ops->setup_data_interface(nand, csline, conf);
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}
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static void atmel_nand_init(struct atmel_nand_controller *nc,
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struct atmel_nand *nand)
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{
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@ -1192,6 +1486,9 @@ static void atmel_nand_init(struct atmel_nand_controller *nc,
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chip->write_buf = atmel_nand_write_buf;
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chip->select_chip = atmel_nand_select_chip;
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if (nc->mck && nc->caps->ops->setup_data_interface)
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chip->setup_data_interface = atmel_nand_setup_data_interface;
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/* Some NANDs require a longer delay than the default one (20us). */
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chip->chip_delay = 40;
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@ -1677,6 +1974,12 @@ static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
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if (nc->caps->legacy_of_bindings)
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return 0;
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nc->mck = of_clk_get(dev->parent->of_node, 0);
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if (IS_ERR(nc->mck)) {
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dev_err(dev, "Failed to retrieve MCK clk\n");
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return PTR_ERR(nc->mck);
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}
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np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
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if (!np) {
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dev_err(dev, "Missing or invalid atmel,smc property\n");
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@ -1983,6 +2286,7 @@ static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
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.remove = atmel_hsmc_nand_controller_remove,
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.ecc_init = atmel_hsmc_nand_ecc_init,
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.nand_init = atmel_hsmc_nand_init,
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.setup_data_interface = atmel_hsmc_nand_setup_data_interface,
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};
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static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
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@ -2037,7 +2341,14 @@ atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
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return 0;
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}
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static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
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/*
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* The SMC reg layout of at91rm9200 is completely different which prevents us
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* from re-using atmel_smc_nand_setup_data_interface() for the
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* ->setup_data_interface() hook.
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* At this point, there's no support for the at91rm9200 SMC IP, so we leave
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* ->setup_data_interface() unassigned.
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*/
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static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
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.probe = atmel_smc_nand_controller_probe,
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.remove = atmel_smc_nand_controller_remove,
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.ecc_init = atmel_nand_ecc_init,
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@ -2045,6 +2356,20 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
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};
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static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
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.ale_offs = BIT(21),
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.cle_offs = BIT(22),
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.ops = &at91rm9200_nc_ops,
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};
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static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
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.probe = atmel_smc_nand_controller_probe,
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.remove = atmel_smc_nand_controller_remove,
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.ecc_init = atmel_nand_ecc_init,
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.nand_init = atmel_smc_nand_init,
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.setup_data_interface = atmel_smc_nand_setup_data_interface,
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};
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static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
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.ale_offs = BIT(21),
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.cle_offs = BIT(22),
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.ops = &atmel_smc_nc_ops,
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@ -2093,7 +2418,7 @@ static const struct of_device_id atmel_nand_controller_of_ids[] = {
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},
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{
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.compatible = "atmel,at91sam9260-nand-controller",
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.data = &atmel_rm9200_nc_caps,
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.data = &atmel_sam9260_nc_caps,
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},
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{
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.compatible = "atmel,at91sam9261-nand-controller",
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