drm/bridge: analogix_dp: add fast link train for eDP
We would meet a short black screen when exit PSR with the full link training, In this case, we should use fast link train instead of full link training. Signed-off-by: zain wang <wzz@rock-chips.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> [dropped header reordering] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20180309222327.18689-6-enric.balletbo@collabora.com
This commit is contained in:
zain wang
Heiko Stuebner
parent
243e398aab
commit
f9d5680596
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@ -15,6 +15,7 @@
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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@ -35,6 +36,8 @@
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#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
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static const bool verify_fast_training;
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struct bridge_init {
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struct i2c_client *client;
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struct device_node *node;
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@ -528,7 +531,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
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{
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int lane, lane_count, retval;
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u32 reg;
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u8 link_align, link_status[2], adjust_request[2];
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u8 link_align, link_status[2], adjust_request[2], spread;
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usleep_range(400, 401);
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@ -571,6 +574,20 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
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dev_dbg(dp->dev, "final lane count = %.2x\n",
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dp->link_train.lane_count);
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retval = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD,
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&spread);
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if (retval != 1) {
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dev_err(dp->dev, "failed to read downspread %d\n",
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retval);
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dp->fast_train_support = false;
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} else {
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dp->fast_train_support =
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(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING) ?
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true : false;
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}
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dev_dbg(dp->dev, "fast link training %s\n",
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dp->fast_train_support ? "supported" : "unsupported");
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/* set enhanced mode if available */
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analogix_dp_set_enhanced_mode(dp);
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dp->link_train.lt_state = FINISHED;
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@ -627,10 +644,12 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
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*lane_count = DPCD_MAX_LANE_COUNT(data);
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}
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static void analogix_dp_init_training(struct analogix_dp_device *dp,
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enum link_lane_count_type max_lane,
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int max_rate)
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static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
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u32 max_lanes, u32 max_rate)
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{
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int retval = 0;
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bool training_finished = false;
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/*
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* MACRO_RST must be applied after the PLL_LOCK to avoid
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* the DP inter pair skew issue for at least 10 us
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@ -656,18 +675,13 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
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}
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/* Setup TX lane count & rate */
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if (dp->link_train.lane_count > max_lane)
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dp->link_train.lane_count = max_lane;
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if (dp->link_train.lane_count > max_lanes)
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dp->link_train.lane_count = max_lanes;
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if (dp->link_train.link_rate > max_rate)
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dp->link_train.link_rate = max_rate;
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/* All DP analog module power up */
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analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
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}
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static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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{
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int retval = 0, training_finished = 0;
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dp->link_train.lt_state = START;
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@ -702,22 +716,88 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
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return retval;
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}
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static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
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u32 count, u32 bwtype)
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static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
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{
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int i;
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int retval;
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int i, ret;
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u8 link_align, link_status[2];
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enum pll_status status;
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for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
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analogix_dp_init_training(dp, count, bwtype);
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retval = analogix_dp_sw_link_training(dp);
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if (retval == 0)
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break;
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analogix_dp_reset_macro(dp);
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usleep_range(100, 110);
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analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
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analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
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for (i = 0; i < dp->link_train.lane_count; i++) {
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analogix_dp_set_lane_link_training(dp,
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dp->link_train.training_lane[i], i);
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}
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return retval;
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ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
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status != PLL_UNLOCKED, 120,
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120 * DP_TIMEOUT_LOOP_COUNT);
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if (ret) {
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DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
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return ret;
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}
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/* source Set training pattern 1 */
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analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
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/* From DP spec, pattern must be on-screen for a minimum 500us */
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usleep_range(500, 600);
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analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
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/* From DP spec, pattern must be on-screen for a minimum 500us */
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usleep_range(500, 600);
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/* TODO: enhanced_mode?*/
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analogix_dp_set_training_pattern(dp, DP_NONE);
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/*
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* Useful for debugging issues with fast link training, disable for more
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* speed
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*/
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if (verify_fast_training) {
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ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
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&link_align);
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if (ret < 0) {
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DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
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ret);
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return ret;
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}
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ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
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2);
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if (ret < 0) {
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DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
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ret);
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return ret;
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}
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if (analogix_dp_clock_recovery_ok(link_status,
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dp->link_train.lane_count)) {
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DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
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analogix_dp_reduce_link_rate(dp);
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return -EIO;
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}
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if (analogix_dp_channel_eq_ok(link_status, link_align,
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dp->link_train.lane_count)) {
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DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
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analogix_dp_reduce_link_rate(dp);
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return -EIO;
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}
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}
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return 0;
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}
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static int analogix_dp_train_link(struct analogix_dp_device *dp)
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{
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if (dp->fast_train_support)
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return analogix_dp_fast_link_train(dp);
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return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
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dp->video_info.max_link_rate);
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}
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static int analogix_dp_config_video(struct analogix_dp_device *dp)
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@ -846,10 +926,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
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DRM_ERROR("failed to disable the panel\n");
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}
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ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
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dp->video_info.max_link_rate);
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ret = readx_poll_timeout(analogix_dp_train_link, dp, ret, !ret, 100,
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DP_TIMEOUT_TRAINING_US * 5);
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if (ret) {
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dev_err(dp->dev, "unable to do link train\n");
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dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
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return;
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}
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@ -20,6 +20,8 @@
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 5
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/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
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#define DP_TIMEOUT_TRAINING_US 22000
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#define DP_TIMEOUT_PSR_LOOP_MS 300
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/* DP_MAX_LANE_COUNT */
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@ -171,6 +173,7 @@ struct analogix_dp_device {
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int hpd_gpio;
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bool force_hpd;
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bool psr_enable;
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bool fast_train_support;
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struct mutex panel_lock;
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bool panel_is_modeset;
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