dmaengine: omap-dma: control start/stop directly
Program the non-cyclic mode DMA start/stop directly, rather than via arch/arm/plat-omap/dma.c. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Russell King
parent
913a2d0c69
commit
fa3ad86ae0
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@ -5,6 +5,7 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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@ -60,6 +61,7 @@ struct omap_desc {
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uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
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uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
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uint8_t periph_port; /* Peripheral port */
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uint16_t cicr; /* CICR value */
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unsigned sglen;
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struct omap_sg sg[0];
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@ -95,6 +97,111 @@ static void omap_dma_desc_free(struct virt_dma_desc *vd)
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kfree(container_of(vd, struct omap_desc, vd));
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}
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static void omap_dma_start(struct omap_chan *c, struct omap_desc *d)
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{
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struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
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uint32_t val;
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if (__dma_omap15xx(od->plat->dma_attr))
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c->plat->dma_write(0, CPC, c->dma_ch);
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else
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c->plat->dma_write(0, CDAC, c->dma_ch);
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if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
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val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
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if (dma_omap1())
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val &= ~(1 << 14);
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val |= c->dma_ch | 1 << 15;
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c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
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} else if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS)
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c->plat->dma_write(c->dma_ch, CLNK_CTRL, c->dma_ch);
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/* Clear CSR */
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if (dma_omap1())
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c->plat->dma_read(CSR, c->dma_ch);
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else
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c->plat->dma_write(~0, CSR, c->dma_ch);
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/* Enable interrupts */
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c->plat->dma_write(d->cicr, CICR, c->dma_ch);
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val = c->plat->dma_read(CCR, c->dma_ch);
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if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING)
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val |= OMAP_DMA_CCR_BUFFERING_DISABLE;
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val |= OMAP_DMA_CCR_EN;
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mb();
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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static void omap_dma_stop(struct omap_chan *c)
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{
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struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device);
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uint32_t val;
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/* disable irq */
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c->plat->dma_write(0, CICR, c->dma_ch);
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/* Clear CSR */
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if (dma_omap1())
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c->plat->dma_read(CSR, c->dma_ch);
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else
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c->plat->dma_write(~0, CSR, c->dma_ch);
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val = c->plat->dma_read(CCR, c->dma_ch);
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if (od->plat->errata & DMA_ERRATA_i541 &&
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val & OMAP_DMA_CCR_SEL_SRC_DST_SYNC) {
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uint32_t sysconfig;
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unsigned i;
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sysconfig = c->plat->dma_read(OCP_SYSCONFIG, c->dma_ch);
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val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK;
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val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
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c->plat->dma_write(val, OCP_SYSCONFIG, c->dma_ch);
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~OMAP_DMA_CCR_EN;
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c->plat->dma_write(val, CCR, c->dma_ch);
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/* Wait for sDMA FIFO to drain */
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for (i = 0; ; i++) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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if (!(val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE)))
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break;
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if (i > 100)
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break;
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udelay(5);
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}
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if (val & (OMAP_DMA_CCR_RD_ACTIVE | OMAP_DMA_CCR_WR_ACTIVE))
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dev_err(c->vc.chan.device->dev,
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"DMA drain did not complete on lch %d\n",
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c->dma_ch);
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c->plat->dma_write(sysconfig, OCP_SYSCONFIG, c->dma_ch);
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} else {
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val &= ~OMAP_DMA_CCR_EN;
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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mb();
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if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) {
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val = c->plat->dma_read(CLNK_CTRL, c->dma_ch);
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if (dma_omap1())
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val |= 1 << 14; /* set the STOP_LNK bit */
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else
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val &= ~(1 << 15); /* Clear the ENABLE_LNK bit */
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c->plat->dma_write(val, CLNK_CTRL, c->dma_ch);
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}
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}
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static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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unsigned idx)
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{
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@ -113,7 +220,7 @@ static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
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c->plat->dma_write(sg->en, CEN, c->dma_ch);
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c->plat->dma_write(sg->fn, CFN, c->dma_ch);
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omap_start_dma(c->dma_ch);
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omap_dma_start(c, d);
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}
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static void omap_dma_start_desc(struct omap_chan *c)
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@ -434,6 +541,12 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->sync_mode = OMAP_DMA_SYNC_FRAME;
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d->sync_type = sync_type;
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d->periph_port = OMAP_DMA_PORT_TIPB;
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d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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if (dma_omap1())
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d->cicr |= OMAP1_DMA_TOUT_IRQ;
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else
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d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
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/*
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* Build our scatterlist entries: each contains the address,
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@ -463,6 +576,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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size_t period_len, enum dma_transfer_direction dir, unsigned long flags,
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void *context)
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{
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struct omap_dmadev *od = to_omap_dma_dev(chan->device);
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struct omap_chan *c = to_omap_dma_chan(chan);
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enum dma_slave_buswidth dev_width;
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struct omap_desc *d;
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@ -519,15 +633,25 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->sg[0].en = period_len / es_bytes[es];
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d->sg[0].fn = buf_len / period_len;
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d->sglen = 1;
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d->cicr = OMAP_DMA_DROP_IRQ;
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if (flags & DMA_PREP_INTERRUPT)
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d->cicr |= OMAP_DMA_FRAME_IRQ;
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if (dma_omap1())
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d->cicr |= OMAP1_DMA_TOUT_IRQ;
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else
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d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
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if (!c->cyclic) {
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c->cyclic = true;
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omap_dma_link_lch(c->dma_ch, c->dma_ch);
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if (flags & DMA_PREP_INTERRUPT)
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omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
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if (__dma_omap15xx(od->plat->dma_attr)) {
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uint32_t val;
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omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
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val = c->plat->dma_read(CCR, c->dma_ch);
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val |= 3 << 8;
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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}
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if (dma_omap2plus()) {
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@ -568,20 +692,27 @@ static int omap_dma_terminate_all(struct omap_chan *c)
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/*
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* Stop DMA activity: we assume the callback will not be called
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* after omap_stop_dma() returns (even if it does, it will see
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* after omap_dma_stop() returns (even if it does, it will see
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* c->desc is NULL and exit.)
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*/
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if (c->desc) {
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c->desc = NULL;
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/* Avoid stopping the dma twice */
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if (!c->paused)
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omap_stop_dma(c->dma_ch);
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omap_dma_stop(c);
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}
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if (c->cyclic) {
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c->cyclic = false;
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c->paused = false;
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omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
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if (__dma_omap15xx(od->plat->dma_attr)) {
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uint32_t val;
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(3 << 8);
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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}
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vchan_get_all_descriptors(&c->vc, &head);
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@ -598,7 +729,7 @@ static int omap_dma_pause(struct omap_chan *c)
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return -EINVAL;
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if (!c->paused) {
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omap_stop_dma(c->dma_ch);
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omap_dma_stop(c);
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c->paused = true;
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}
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@ -612,7 +743,7 @@ static int omap_dma_resume(struct omap_chan *c)
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return -EINVAL;
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if (c->paused) {
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omap_start_dma(c->dma_ch);
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omap_dma_start(c, c->desc);
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c->paused = false;
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}
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