mtd: nand: denali: switch over to cmd_ctrl instead of cmdfunc
The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc(). We also see /* TODO: Read OOB data */ comment. It would be possible to add more commands along with the current implementation, but having ->cmd_ctrl() seems a better approach from the discussion with Boris [1]. Rely on the default ->cmdfunc() from the framework and implement the driver's own ->cmd_ctrl(). This transition also fixes NAND_CMD_STATUS and NAND_CMD_PARAM handling. NAND_CMD_STATUS was just faked by the register read, so the only valid bit was the WP bit. NAND_CMD_PARAM was completely broken; not only the command sent on the bus was NAND_CMD_STATUS instead of NAND_CMD_PARAM, but also the driver was only reading 8 bytes, while the parameter page contains several hundreds of bytes. Also add ->write_byte(), which is needed for write direction commands, ->read/write_buf(16), which will be used some commits later. ->read_word() is not used for now, but the core may call it in the future. Now, this driver can drop nand_onfi_get_set_features_notsupp(). [1] https://lkml.org/lkml/2017/3/15/97 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Masahiro Yamada
Boris Brezillon
parent
c19e31d0a3
commit
fa6134e545
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@ -85,43 +85,6 @@ static void index_addr(struct denali_nand_info *denali,
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iowrite32(data, denali->flash_mem + 0x10);
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}
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/* Perform an indexed read of the device */
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static void index_addr_read_data(struct denali_nand_info *denali,
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uint32_t address, uint32_t *pdata)
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{
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iowrite32(address, denali->flash_mem);
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*pdata = ioread32(denali->flash_mem + 0x10);
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}
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/*
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* We need to buffer some data for some of the NAND core routines.
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* The operations manage buffering that data.
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*/
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static void reset_buf(struct denali_nand_info *denali)
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{
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denali->buf.head = denali->buf.tail = 0;
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}
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static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
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{
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denali->buf.buf[denali->buf.tail++] = byte;
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}
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/* reads the status of the device */
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static void read_status(struct denali_nand_info *denali)
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{
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uint32_t cmd;
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/* initialize the data buffer to store status */
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reset_buf(denali);
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cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
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if (cmd)
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write_byte_to_buf(denali, NAND_STATUS_WP);
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else
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write_byte_to_buf(denali, 0);
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}
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/* Reset the flash controller */
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static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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{
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@ -268,20 +231,16 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
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return denali->irq_status;
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}
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/* resets a specific device connected to the core */
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static void reset_bank(struct denali_nand_info *denali)
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static uint32_t denali_check_irq(struct denali_nand_info *denali)
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{
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unsigned long flags;
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uint32_t irq_status;
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denali_reset_irq(denali);
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spin_lock_irqsave(&denali->irq_lock, flags);
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irq_status = denali->irq_status;
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spin_unlock_irqrestore(&denali->irq_lock, flags);
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iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
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irq_status = denali_wait_for_irq(denali,
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INTR__RST_COMP | INTR__TIME_OUT);
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if (!(irq_status & INTR__RST_COMP))
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dev_err(denali->dev, "reset bank failed.\n");
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return irq_status;
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}
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/*
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@ -302,6 +261,105 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
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iowrite32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
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}
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static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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int i;
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iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem);
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for (i = 0; i < len; i++)
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buf[i] = ioread32(denali->flash_mem + 0x10);
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}
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static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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int i;
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iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem);
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for (i = 0; i < len; i++)
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iowrite32(buf[i], denali->flash_mem + 0x10);
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}
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static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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uint16_t *buf16 = (uint16_t *)buf;
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int i;
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iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem);
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for (i = 0; i < len / 2; i++)
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buf16[i] = ioread32(denali->flash_mem + 0x10);
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}
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static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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const uint16_t *buf16 = (const uint16_t *)buf;
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int i;
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iowrite32(MODE_11 | BANK(denali->flash_bank) | 2, denali->flash_mem);
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for (i = 0; i < len / 2; i++)
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iowrite32(buf16[i], denali->flash_mem + 0x10);
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}
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static uint8_t denali_read_byte(struct mtd_info *mtd)
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{
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uint8_t byte;
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denali_read_buf(mtd, &byte, 1);
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return byte;
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}
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static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
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{
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denali_write_buf(mtd, &byte, 1);
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}
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static uint16_t denali_read_word(struct mtd_info *mtd)
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{
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uint16_t word;
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denali_read_buf16(mtd, (uint8_t *)&word, 2);
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return word;
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}
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static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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uint32_t type;
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if (ctrl & NAND_CLE)
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type = 0;
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else if (ctrl & NAND_ALE)
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type = 1;
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else
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return;
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/*
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* Some commands are followed by chip->dev_ready or chip->waitfunc.
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* irq_status must be cleared here to catch the R/B# interrupt later.
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*/
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if (ctrl & NAND_CTRL_CHANGE)
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denali_reset_irq(denali);
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index_addr(denali, MODE_11 | BANK(denali->flash_bank) | type, dat);
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}
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static int denali_dev_ready(struct mtd_info *mtd)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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return !!(denali_check_irq(denali) & INTR__INT_ACT);
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}
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/*
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* sends a pipeline command operation to the controller. See the Denali NAND
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* controller's user guide for more information (section 4.2.3.6).
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@ -844,17 +902,6 @@ static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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return 0;
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}
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static uint8_t denali_read_byte(struct mtd_info *mtd)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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uint8_t result = 0xff;
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if (denali->buf.head < denali->buf.tail)
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result = denali->buf.buf[denali->buf.head++];
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return result;
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}
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static void denali_select_chip(struct mtd_info *mtd, int chip)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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@ -864,7 +911,13 @@ static void denali_select_chip(struct mtd_info *mtd, int chip)
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static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
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{
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return 0;
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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uint32_t irq_status;
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/* R/B# pin transitioned from low to high? */
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irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
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return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
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}
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static int denali_erase(struct mtd_info *mtd, int page)
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@ -885,45 +938,6 @@ static int denali_erase(struct mtd_info *mtd, int page)
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return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
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}
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static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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int page)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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uint32_t addr, id;
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int i;
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switch (cmd) {
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case NAND_CMD_STATUS:
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read_status(denali);
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break;
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case NAND_CMD_READID:
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case NAND_CMD_PARAM:
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reset_buf(denali);
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/*
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* sometimes ManufactureId read from register is not right
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* e.g. some of Micron MT29F32G08QAA MLC NAND chips
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* So here we send READID cmd to NAND insteand
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*/
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addr = MODE_11 | BANK(denali->flash_bank);
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index_addr(denali, addr | 0, 0x90);
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index_addr(denali, addr | 1, col);
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for (i = 0; i < 8; i++) {
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index_addr_read_data(denali, addr | 2, &id);
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write_byte_to_buf(denali, id);
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}
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break;
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case NAND_CMD_RESET:
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reset_bank(denali);
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break;
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case NAND_CMD_READOOB:
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/* TODO: Read OOB data */
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break;
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default:
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pr_err(": unsupported command received 0x%x\n", cmd);
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break;
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}
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}
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#define DIV_ROUND_DOWN_ULL(ll, d) \
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({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
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@ -1239,12 +1253,6 @@ int denali_init(struct denali_nand_info *denali)
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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/* allocate a temporary buffer for nand_scan_ident() */
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denali->buf.buf = devm_kzalloc(denali->dev, PAGE_SIZE,
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GFP_DMA | GFP_KERNEL);
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if (!denali->buf.buf)
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return -ENOMEM;
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mtd->dev.parent = denali->dev;
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denali_hw_init(denali);
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denali_drv_init(denali);
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@ -1268,11 +1276,12 @@ int denali_init(struct denali_nand_info *denali)
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/* register the driver with the NAND core subsystem */
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chip->select_chip = denali_select_chip;
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chip->cmdfunc = denali_cmdfunc;
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chip->read_byte = denali_read_byte;
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chip->write_byte = denali_write_byte;
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chip->read_word = denali_read_word;
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chip->cmd_ctrl = denali_cmd_ctrl;
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chip->dev_ready = denali_dev_ready;
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chip->waitfunc = denali_waitfunc;
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chip->onfi_set_features = nand_onfi_get_set_features_notsupp;
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chip->onfi_get_features = nand_onfi_get_set_features_notsupp;
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/* clk rate info is needed for setup_data_interface */
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if (denali->clk_x_rate)
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@ -1287,8 +1296,6 @@ int denali_init(struct denali_nand_info *denali)
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if (ret)
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goto disable_irq;
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/* allocate the right size buffer now */
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devm_kfree(denali->dev, denali->buf.buf);
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denali->buf.buf = devm_kzalloc(denali->dev,
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mtd->writesize + mtd->oobsize,
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GFP_KERNEL);
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@ -1358,6 +1365,13 @@ int denali_init(struct denali_nand_info *denali)
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mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
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if (chip->options & NAND_BUSWIDTH_16) {
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chip->read_buf = denali_read_buf16;
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chip->write_buf = denali_write_buf16;
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} else {
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chip->read_buf = denali_read_buf;
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chip->write_buf = denali_write_buf;
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}
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chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
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chip->ecc.read_page = denali_read_page;
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chip->ecc.read_page_raw = denali_read_page_raw;
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@ -306,8 +306,6 @@
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#define MODE_11 0x0C000000
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struct nand_buf {
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int head;
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int tail;
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uint8_t *buf;
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dma_addr_t dma_buf;
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};
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