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usb: dwc3: Add SoftReset PHY synchonization delay

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From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
Thinh Nguyen 2018-03-16 15:33:48 -07:00 committed by Felipe Balbi
parent cabdf83dad
commit fab3833338
1 changed files with 12 additions and 1 deletions
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13
drivers/usb/dwc3/core.c
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@ -244,7 +244,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
return 0;
goto done;
udelay(1);
} while (--retries);
@ -253,6 +253,17 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
phy_exit(dwc->usb2_generic_phy);
return -ETIMEDOUT;
done:
/*
* For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
* we must wait at least 50ms before accessing the PHY domain
* (synchronization delay). DWC_usb31 programming guide section 1.3.2.
*/
if (dwc3_is_usb31(dwc))
msleep(50);
return 0;
}
/*