drm/msm: resync generated headers
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
2e54a92ff2
commit
facb4f4e7f
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@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -202,6 +203,12 @@ enum a2xx_rb_copy_sample_select {
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SAMPLE_0123 = 6,
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};
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enum adreno_mmu_clnt_beh {
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BEH_NEVR = 0,
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BEH_TRAN_RNG = 1,
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BEH_TRAN_FLT = 2,
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};
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enum sq_tex_clamp {
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SQ_TEX_WRAP = 0,
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SQ_TEX_MIRROR = 1,
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@ -238,6 +245,92 @@ enum sq_tex_filter {
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#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
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#define REG_A2XX_MH_MMU_CONFIG 0x00000040
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#define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
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#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
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#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
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#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
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static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
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#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
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#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
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#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
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#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
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#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
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#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
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static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
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#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
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static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
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#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
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static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
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#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
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static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
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}
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#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
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#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
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static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
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{
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return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
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}
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#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
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#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
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#define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043
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#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
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#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
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#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
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#define REG_A2XX_MH_MMU_MPU_END 0x00000047
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#define REG_A2XX_NQWAIT_UNTIL 0x00000394
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#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
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#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
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@ -276,20 +369,6 @@ enum sq_tex_filter {
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#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
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#define REG_A2XX_CP_ST_BASE 0x0000044d
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#define REG_A2XX_CP_ST_BUFSZ 0x0000044e
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#define REG_A2XX_CP_IB1_BASE 0x00000458
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#define REG_A2XX_CP_IB1_BUFSZ 0x00000459
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#define REG_A2XX_CP_IB2_BASE 0x0000045a
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#define REG_A2XX_CP_IB2_BUFSZ 0x0000045b
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#define REG_A2XX_CP_STAT 0x0000047f
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#define REG_A2XX_RBBM_STATUS 0x000005d0
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#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f
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#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0
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@ -808,6 +887,12 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
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#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
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#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
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#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
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#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
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#define REG_A2XX_RB_DEPTHCONTROL 0x00002200
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#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001
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#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002
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@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@ -292,6 +293,8 @@ enum a3xx_tex_type {
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#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
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#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
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#define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
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#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
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#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
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@ -304,6 +307,8 @@ enum a3xx_tex_type {
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#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
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#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
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#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
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#define REG_A3XX_RBBM_INT_0_MASK 0x00000063
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@ -937,13 +942,13 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
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return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
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}
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#define REG_A3XX_UNKNOWN_20E8 0x000020e8
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#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
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#define REG_A3XX_UNKNOWN_20E9 0x000020e9
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#define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
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#define REG_A3XX_UNKNOWN_20EA 0x000020ea
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#define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
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#define REG_A3XX_UNKNOWN_20EB 0x000020eb
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#define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
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#define REG_A3XX_RB_COPY_CONTROL 0x000020ec
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#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
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@ -1026,7 +1031,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
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#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
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#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
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#define REG_A3XX_UNKNOWN_2101 0x00002101
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#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
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#define REG_A3XX_RB_DEPTH_INFO 0x00002102
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#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
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@ -1103,11 +1108,11 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
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return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
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}
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#define REG_A3XX_UNKNOWN_2105 0x00002105
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#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
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#define REG_A3XX_UNKNOWN_2106 0x00002106
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#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106
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#define REG_A3XX_UNKNOWN_2107 0x00002107
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#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107
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#define REG_A3XX_RB_STENCILREFMASK 0x00002108
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#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
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@ -1149,20 +1154,31 @@ static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
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return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
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}
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#define REG_A3XX_PA_SC_WINDOW_OFFSET 0x0000210e
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#define A3XX_PA_SC_WINDOW_OFFSET_X__MASK 0x0000ffff
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#define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
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static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val)
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#define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
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#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
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#define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
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#define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
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#define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
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static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
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{
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return ((val) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK;
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return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
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}
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#define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK 0xffff0000
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#define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
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static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val)
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#define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
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#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
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static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
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{
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return ((val) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK;
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return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
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}
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#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
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#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
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#define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
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#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
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|
||||
#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
|
||||
|
||||
#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
|
||||
|
|
@ -1309,6 +1325,8 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
|
|||
|
||||
#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
|
||||
|
||||
#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
|
||||
|
||||
#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
|
||||
|
||||
#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
|
||||
|
|
@ -1491,12 +1509,13 @@ static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0
|
|||
|
||||
#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
|
||||
#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
|
||||
#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x000c0000
|
||||
#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
|
||||
#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
|
||||
static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
|
||||
}
|
||||
#define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
|
||||
#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
|
||||
#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
|
||||
static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
|
||||
|
|
@ -1669,7 +1688,7 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
|
||||
#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
|
||||
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG 0x000022d6
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
|
||||
|
||||
#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
|
||||
|
||||
|
|
@ -1772,7 +1791,7 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
|
|||
|
||||
#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
|
||||
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG 0x000022e4
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
|
||||
|
||||
#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
|
||||
|
||||
|
|
@ -1943,6 +1962,9 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00
|
|||
|
||||
static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
|
||||
|
||||
#define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
|
||||
#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
|
||||
|
||||
#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
|
||||
|
|
@ -1953,7 +1975,7 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
|
|||
|
||||
#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
|
||||
|
||||
#define REG_A3XX_UNKNOWN_0C81 0x00000c81
|
||||
#define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
|
||||
|
||||
#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
|
||||
|
||||
|
|
@ -1975,22 +1997,24 @@ static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x000
|
|||
|
||||
#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
|
||||
|
||||
#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
|
||||
|
||||
#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
|
||||
|
||||
#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
|
||||
|
||||
#define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0
|
||||
#define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff
|
||||
#define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val)
|
||||
#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
|
||||
#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
|
||||
#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
|
||||
static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK;
|
||||
return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
|
||||
}
|
||||
#define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK 0x0fffc000
|
||||
#define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT 14
|
||||
static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val)
|
||||
#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
|
||||
#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
|
||||
static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
|
||||
{
|
||||
return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK;
|
||||
return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
|
||||
|
|
@ -2088,6 +2112,14 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
|
|||
|
||||
#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
|
||||
|
||||
#define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
|
||||
|
||||
#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
|
||||
|
||||
#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
|
||||
|
||||
#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
|
||||
|
||||
#define REG_A3XX_TEX_SAMP_0 0x00000000
|
||||
#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
|
||||
#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
|
||||
|
|
@ -2123,6 +2155,18 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
|
|||
#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
|
||||
|
||||
#define REG_A3XX_TEX_SAMP_1 0x00000001
|
||||
#define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
|
||||
#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
|
||||
static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
|
||||
{
|
||||
return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
|
||||
}
|
||||
#define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
|
||||
#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
|
||||
static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
|
||||
{
|
||||
return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
|
||||
}
|
||||
|
||||
#define REG_A3XX_TEX_CONST_0 0x00000000
|
||||
#define A3XX_TEX_CONST_0_TILED 0x00000001
|
||||
|
|
|
|||
|
|
@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -115,96 +116,6 @@ enum adreno_rb_depth_format {
|
|||
DEPTHX_24_8 = 1,
|
||||
};
|
||||
|
||||
enum adreno_mmu_clnt_beh {
|
||||
BEH_NEVR = 0,
|
||||
BEH_TRAN_RNG = 1,
|
||||
BEH_TRAN_FLT = 2,
|
||||
};
|
||||
|
||||
#define REG_AXXX_MH_MMU_CONFIG 0x00000040
|
||||
#define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
|
||||
#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
|
||||
#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
|
||||
#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
|
||||
#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
|
||||
#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
|
||||
#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
|
||||
#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
|
||||
#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
|
||||
static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
|
||||
{
|
||||
return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_MH_MMU_VA_RANGE 0x00000041
|
||||
|
||||
#define REG_AXXX_MH_MMU_PT_BASE 0x00000042
|
||||
|
||||
#define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043
|
||||
|
||||
#define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044
|
||||
|
||||
#define REG_AXXX_MH_MMU_INVALIDATE 0x00000045
|
||||
|
||||
#define REG_AXXX_MH_MMU_MPU_BASE 0x00000046
|
||||
|
||||
#define REG_AXXX_MH_MMU_MPU_END 0x00000047
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
|
|
@ -275,6 +186,18 @@ static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
|
||||
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
|
||||
}
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
|
||||
#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
|
||||
static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
|
||||
{
|
||||
return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
|
||||
#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
|
||||
|
|
@ -402,6 +325,36 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
|||
return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
|
||||
}
|
||||
|
||||
#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
|
||||
|
||||
#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
|
||||
|
||||
#define REG_AXXX_CP_ST_BASE 0x0000044d
|
||||
|
||||
#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
|
||||
|
||||
#define REG_AXXX_CP_MEQ_STAT 0x0000044f
|
||||
|
||||
#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
|
||||
|
||||
#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
|
||||
|
||||
#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
|
||||
|
||||
#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
|
||||
|
||||
#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
|
||||
|
||||
#define REG_AXXX_CP_IB1_BASE 0x00000458
|
||||
|
||||
#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
|
||||
|
||||
#define REG_AXXX_CP_IB2_BASE 0x0000045a
|
||||
|
||||
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
|
||||
|
||||
#define REG_AXXX_CP_STAT 0x0000047f
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
|
||||
|
|
@ -418,6 +371,26 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
|||
|
||||
#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
|
||||
|
||||
#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
|
||||
|
||||
#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
|
||||
|
|
@ -428,5 +401,11 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
|||
|
||||
#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
|
||||
|
||||
#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
|
||||
|
||||
|
||||
#endif /* ADRENO_COMMON_XML */
|
||||
|
|
|
|||
|
|
@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -66,13 +67,15 @@ enum vgt_event_type {
|
|||
|
||||
enum pc_di_primtype {
|
||||
DI_PT_NONE = 0,
|
||||
DI_PT_POINTLIST = 1,
|
||||
DI_PT_POINTLIST_A2XX = 1,
|
||||
DI_PT_LINELIST = 2,
|
||||
DI_PT_LINESTRIP = 3,
|
||||
DI_PT_TRILIST = 4,
|
||||
DI_PT_TRIFAN = 5,
|
||||
DI_PT_TRISTRIP = 6,
|
||||
DI_PT_LINELOOP = 7,
|
||||
DI_PT_RECTLIST = 8,
|
||||
DI_PT_POINTLIST_A3XX = 9,
|
||||
DI_PT_QUADLIST = 13,
|
||||
DI_PT_QUADSTRIP = 14,
|
||||
DI_PT_POLYGON = 15,
|
||||
|
|
@ -119,7 +122,7 @@ enum adreno_pm4_type3_packets {
|
|||
CP_WAIT_FOR_IDLE = 38,
|
||||
CP_WAIT_REG_MEM = 60,
|
||||
CP_WAIT_REG_EQ = 82,
|
||||
CP_WAT_REG_GTE = 83,
|
||||
CP_WAIT_REG_GTE = 83,
|
||||
CP_WAIT_UNTIL_READ = 92,
|
||||
CP_WAIT_IB_PFD_COMPLETE = 93,
|
||||
CP_REG_RMW = 33,
|
||||
|
|
@ -151,7 +154,6 @@ enum adreno_pm4_type3_packets {
|
|||
CP_CONTEXT_UPDATE = 94,
|
||||
CP_INTERRUPT = 64,
|
||||
CP_IM_STORE = 44,
|
||||
CP_SET_BIN_BASE_OFFSET = 75,
|
||||
CP_SET_DRAW_INIT_FLAGS = 75,
|
||||
CP_SET_PROTECTED_MODE = 95,
|
||||
CP_LOAD_STATE = 48,
|
||||
|
|
@ -159,6 +161,16 @@ enum adreno_pm4_type3_packets {
|
|||
CP_COND_INDIRECT_BUFFER_PFD = 50,
|
||||
CP_INDIRECT_BUFFER_PFE = 63,
|
||||
CP_SET_BIN = 76,
|
||||
CP_TEST_TWO_MEMS = 113,
|
||||
CP_WAIT_FOR_ME = 19,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
IN_INSTR_MATCH = 71,
|
||||
IN_CONST_PREFETCH = 73,
|
||||
IN_INCR_UPDT_STATE = 85,
|
||||
IN_INCR_UPDT_CONST = 86,
|
||||
IN_INCR_UPDT_INSTR = 87,
|
||||
};
|
||||
|
||||
enum adreno_state_block {
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -212,6 +214,20 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state
|
|||
#define REG_HDMI_HDCP_RESET 0x00000130
|
||||
#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO0 0x0000016c
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO1 0x00000170
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO2 0x00000174
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO3 0x00000178
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO4 0x0000017c
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO5 0x00000180
|
||||
|
||||
#define REG_HDMI_VENSPEC_INFO6 0x00000184
|
||||
|
||||
#define REG_HDMI_AUDIO_CFG 0x000001d0
|
||||
#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
|
||||
#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
|
||||
|
|
@ -235,6 +251,9 @@ static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
|
|||
return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
|
||||
}
|
||||
|
||||
#define REG_HDMI_DDC_ARBITRATION 0x00000210
|
||||
#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
|
||||
|
||||
#define REG_HDMI_DDC_INT_CTRL 0x00000214
|
||||
#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
|
||||
#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
|
||||
|
|
@ -340,6 +359,20 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
|
|||
return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
|
||||
}
|
||||
|
||||
#define REG_HDMI_CEC_STATUS 0x00000298
|
||||
|
||||
#define REG_HDMI_CEC_INT 0x0000029c
|
||||
|
||||
#define REG_HDMI_CEC_ADDR 0x000002a0
|
||||
|
||||
#define REG_HDMI_CEC_TIME 0x000002a4
|
||||
|
||||
#define REG_HDMI_CEC_REFTIMER 0x000002a8
|
||||
|
||||
#define REG_HDMI_CEC_RD_DATA 0x000002ac
|
||||
|
||||
#define REG_HDMI_CEC_RD_FILTER 0x000002b0
|
||||
|
||||
#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
|
||||
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
|
||||
#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
|
||||
|
|
@ -410,17 +443,33 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
|
|||
#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
|
||||
#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
|
||||
|
||||
#define REG_HDMI_AUD_INT 0x000002cc
|
||||
#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
|
||||
#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
|
||||
#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
|
||||
#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
|
||||
|
||||
#define REG_HDMI_PHY_CTRL 0x000002d4
|
||||
#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
|
||||
#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
|
||||
#define HDMI_PHY_CTRL_SW_RESET 0x00000004
|
||||
#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
|
||||
|
||||
#define REG_HDMI_AUD_INT 0x000002cc
|
||||
#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
|
||||
#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
|
||||
#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
|
||||
#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
|
||||
#define REG_HDMI_CEC_WR_RANGE 0x000002dc
|
||||
|
||||
#define REG_HDMI_CEC_RD_RANGE 0x000002e0
|
||||
|
||||
#define REG_HDMI_VERSION 0x000002e4
|
||||
|
||||
#define REG_HDMI_CEC_COMPL_CTL 0x00000360
|
||||
|
||||
#define REG_HDMI_CEC_RD_START_RANGE 0x00000364
|
||||
|
||||
#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
|
||||
|
||||
#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
|
||||
|
||||
#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
|
||||
|
||||
#define REG_HDMI_8x60_PHY_REG0 0x00000300
|
||||
#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
|
||||
|
|
@ -504,5 +553,23 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
|
|||
|
||||
#define REG_HDMI_8960_PHY_REG12 0x00000430
|
||||
|
||||
#define REG_HDMI_8x74_ANA_CFG0 0x00000000
|
||||
|
||||
#define REG_HDMI_8x74_ANA_CFG1 0x00000004
|
||||
|
||||
#define REG_HDMI_8x74_PD_CTRL0 0x00000010
|
||||
|
||||
#define REG_HDMI_8x74_PD_CTRL1 0x00000014
|
||||
|
||||
#define REG_HDMI_8x74_BIST_CFG0 0x00000034
|
||||
|
||||
#define REG_HDMI_8x74_BIST_PATN0 0x0000003c
|
||||
|
||||
#define REG_HDMI_8x74_BIST_PATN1 0x00000040
|
||||
|
||||
#define REG_HDMI_8x74_BIST_PATN2 0x00000044
|
||||
|
||||
#define REG_HDMI_8x74_BIST_PATN3 0x00000048
|
||||
|
||||
|
||||
#endif /* HDMI_XML */
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
@ -42,27 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
*/
|
||||
|
||||
|
||||
enum mdp4_bpc {
|
||||
BPC1 = 0,
|
||||
BPC5 = 1,
|
||||
BPC6 = 2,
|
||||
BPC8 = 3,
|
||||
};
|
||||
|
||||
enum mdp4_bpc_alpha {
|
||||
BPC1A = 0,
|
||||
BPC4A = 1,
|
||||
BPC6A = 2,
|
||||
BPC8A = 3,
|
||||
};
|
||||
|
||||
enum mdp4_alpha_type {
|
||||
FG_CONST = 0,
|
||||
BG_CONST = 1,
|
||||
FG_PIXEL = 2,
|
||||
BG_PIXEL = 3,
|
||||
};
|
||||
|
||||
enum mdp4_pipe {
|
||||
VG1 = 0,
|
||||
VG2 = 1,
|
||||
|
|
@ -79,15 +60,6 @@ enum mdp4_mixer {
|
|||
MIXER2 = 2,
|
||||
};
|
||||
|
||||
enum mdp4_mixer_stage_id {
|
||||
STAGE_UNUSED = 0,
|
||||
STAGE_BASE = 1,
|
||||
STAGE0 = 2,
|
||||
STAGE1 = 3,
|
||||
STAGE2 = 4,
|
||||
STAGE3 = 5,
|
||||
};
|
||||
|
||||
enum mdp4_intf {
|
||||
INTF_LCDC_DTV = 0,
|
||||
INTF_DSI_VIDEO = 1,
|
||||
|
|
@ -194,56 +166,56 @@ static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
|
|||
#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
|
||||
#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
|
||||
}
|
||||
|
|
@ -254,56 +226,56 @@ static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id va
|
|||
#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
|
||||
}
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
|
||||
#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val)
|
||||
static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
|
||||
{
|
||||
return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
|
||||
}
|
||||
|
|
@ -369,7 +341,7 @@ static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x
|
|||
static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
|
||||
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
|
||||
#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
|
||||
{
|
||||
return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
|
||||
}
|
||||
|
|
@ -377,7 +349,7 @@ static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
|
|||
#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
|
||||
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
|
||||
#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val)
|
||||
static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
|
||||
{
|
||||
return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
|
||||
}
|
||||
|
|
@ -472,19 +444,19 @@ static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __of
|
|||
static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
|
||||
#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
|
||||
#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
|
||||
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
|
||||
}
|
||||
#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
|
||||
#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
|
||||
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
|
||||
}
|
||||
#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
|
||||
#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
|
||||
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
|
||||
}
|
||||
|
|
@ -710,25 +682,25 @@ static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
|
|||
static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
|
||||
#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
|
||||
#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
|
||||
#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
|
||||
#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
|
||||
}
|
||||
#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
|
||||
#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val)
|
||||
static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
|
||||
{
|
||||
return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -232,7 +232,7 @@ static void blend_setup(struct drm_crtc *crtc)
|
|||
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
||||
int i, ovlp = mdp4_crtc->ovlp;
|
||||
uint32_t mixer_cfg = 0;
|
||||
static const enum mdp4_mixer_stage_id stages[] = {
|
||||
static const enum mdp_mixer_stage_id stages[] = {
|
||||
STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
|
||||
};
|
||||
/* statically (for now) map planes to mixer stage (z-order): */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/regulator/consumer.h>
|
||||
|
||||
#include "msm_drv.h"
|
||||
#include "mdp/mdp_common.xml.h"
|
||||
#include "mdp4.xml.h"
|
||||
|
||||
|
||||
|
|
@ -75,8 +76,8 @@ struct mdp4_platform_config {
|
|||
|
||||
struct mdp4_format {
|
||||
struct msm_format base;
|
||||
enum mdp4_bpc bpc_r, bpc_g, bpc_b;
|
||||
enum mdp4_bpc_alpha bpc_a;
|
||||
enum mdp_bpc bpc_r, bpc_g, bpc_b;
|
||||
enum mdp_bpc_alpha bpc_a;
|
||||
uint8_t unpack[4];
|
||||
bool alpha_enable, unpack_tight;
|
||||
uint8_t cpp, unpack_count;
|
||||
|
|
@ -134,7 +135,7 @@ static inline uint32_t dma2err(enum mdp4_dma dma)
|
|||
}
|
||||
|
||||
static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
|
||||
enum mdp4_mixer_stage_id stage)
|
||||
enum mdp_mixer_stage_id stage)
|
||||
{
|
||||
uint32_t mixer_cfg = 0;
|
||||
|
||||
|
|
|
|||
1036
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
Normal file
1036
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
Normal file
File diff suppressed because it is too large
Load diff
78
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
Normal file
78
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
#ifndef MDP_COMMON_XML
|
||||
#define MDP_COMMON_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
|
||||
|
||||
Copyright (C) 2013 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
enum mdp_mixer_stage_id {
|
||||
STAGE_UNUSED = 0,
|
||||
STAGE_BASE = 1,
|
||||
STAGE0 = 2,
|
||||
STAGE1 = 3,
|
||||
STAGE2 = 4,
|
||||
STAGE3 = 5,
|
||||
};
|
||||
|
||||
enum mdp_alpha_type {
|
||||
FG_CONST = 0,
|
||||
BG_CONST = 1,
|
||||
FG_PIXEL = 2,
|
||||
BG_PIXEL = 3,
|
||||
};
|
||||
|
||||
enum mdp_bpc {
|
||||
BPC1 = 0,
|
||||
BPC5 = 1,
|
||||
BPC6 = 2,
|
||||
BPC8 = 3,
|
||||
};
|
||||
|
||||
enum mdp_bpc_alpha {
|
||||
BPC1A = 0,
|
||||
BPC4A = 1,
|
||||
BPC6A = 2,
|
||||
BPC8A = 3,
|
||||
};
|
||||
|
||||
|
||||
#endif /* MDP_COMMON_XML */
|
||||
Loading…
Reference in a new issue