ARM: dts: rockchip: add core rk3036 dtsi
Initial release for rk3036 shared dtsi. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>hifive-unleashed-5.1
Xing Zheng
Heiko Stuebner
parent
20aef5a220
commit
faea098e18
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@ -0,0 +1,554 @@
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/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3036-cru.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3036";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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mshc0 = &emmc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3036-smp";
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x2000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x00 0x10>;
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};
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};
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gic: interrupt-controller@10139000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x10139000 0x1000>,
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<0x1013a000 0x1000>,
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<0x1013c000 0x2000>,
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<0x1013e000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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usb_otg: usb@10180000 {
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compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG0>;
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clock-names = "otg";
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dr_mode = "otg";
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g-np-tx-fifo-size = <16>;
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g-rx-fifo-size = <275>;
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g-tx-fifo-size = <256 128 128 64 64 32>;
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g-use-dma;
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status = "disabled";
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};
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usb_host: usb@101c0000 {
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compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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reg = <0x101c0000 0x40000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG1>;
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clock-names = "otg";
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dr_mode = "host";
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status = "disabled";
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};
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emmc: dwmmc@1021c000 {
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compatible = "rockchip,rk3288-dw-mshc";
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reg = <0x1021c000 0x4000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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broken-cd;
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bus-width = <8>;
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cap-mmc-highspeed;
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clock-frequency = <37500000>;
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clock-freq-min-max = <400000 37500000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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default-sample-phase = <158>;
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disable-wp;
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dmas = <&pdma 12>;
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dma-names = "rx-tx";
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fifo-depth = <0x100>;
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mmc-ddr-1_8v;
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non-removable;
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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status = "disabled";
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};
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i2s: i2s@10220000 {
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compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
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reg = <0x10220000 0x4000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>;
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dmas = <&pdma 0>, <&pdma 1>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s_bus>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3036-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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grf: syscon@20008000 {
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compatible = "rockchip,rk3036-grf", "syscon";
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reg = <0x20008000 0x1000>;
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};
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acodec: acodec-ana@20030000 {
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compatible = "rk3036-codec";
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reg = <0x20030000 0x4000>;
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rockchip,grf = <&grf>;
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clock-names = "acodec_pclk";
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clocks = <&cru PCLK_ACODEC>;
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status = "disabled";
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};
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timer: timer@20044000 {
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compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
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reg = <0x20044000 0x20>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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pwm0: pwm@20050000 {
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compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
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reg = <0x20050000 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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status = "disabled";
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};
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pwm1: pwm@20050010 {
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compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
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reg = <0x20050010 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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status = "disabled";
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};
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pwm2: pwm@20050020 {
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compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
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reg = <0x20050020 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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status = "disabled";
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};
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pwm3: pwm@20050030 {
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compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
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reg = <0x20050030 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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status = "disabled";
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};
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i2c1: i2c@20056000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0x20056000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c2: i2c@2005a000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0x2005a000 0x1000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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uart0: serial@20060000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20060000 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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status = "disabled";
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};
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uart1: serial@20064000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20064000 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "disabled";
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};
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uart2: serial@20068000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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status = "disabled";
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};
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i2c0: i2c@20072000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0x20072000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3036-pinctrl";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@2007c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2007c000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@20084000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <0 1 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <0 27 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
/*
|
||||
* We run eMMC at max speed; bump up drive strength.
|
||||
* We also have external pulls, so disable the internal ones.
|
||||
*/
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
i2c1_xfer: i2c1-xfer {
|
||||
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<0 3 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
i2c2_xfer: i2c2-xfer {
|
||||
rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s {
|
||||
i2s_bus: i2s-bus {
|
||||
rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 1 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<0 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart1 */
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue