Merge branch 'clk-renesas' into clk-next
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...hifive-unleashed-5.1
Stephen Boyd
commit
faff3d8e85
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@ -13,9 +13,13 @@ They provide the following functionalities:
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Required Properties:
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- compatible: Must be one of:
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- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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- "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
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- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
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- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
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@ -35,12 +39,13 @@ Required Properties:
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,
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r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,
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r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
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r8a7794)
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- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
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r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
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r8a77995)
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- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
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r8a7793, r8a7794)
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- #clock-cells: Must be 2
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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@ -5,11 +5,14 @@ config CLK_RENESAS
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default y if ARCH_RENESAS
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select CLK_EMEV2 if ARCH_EMEV2
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select CLK_RZA1 if ARCH_R7S72100
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select CLK_R7S9210 if ARCH_R7S9210
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select CLK_R8A73A4 if ARCH_R8A73A4
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select CLK_R8A7740 if ARCH_R8A7740
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select CLK_R8A7743 if ARCH_R8A7743
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select CLK_R8A7743 if ARCH_R8A7743 || ARCH_R8A7744
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select CLK_R8A7745 if ARCH_R8A7745
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select CLK_R8A77470 if ARCH_R8A77470
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select CLK_R8A774A1 if ARCH_R8A774A1
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select CLK_R8A774C0 if ARCH_R8A774C0
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select CLK_R8A7778 if ARCH_R8A7778
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select CLK_R8A7779 if ARCH_R8A7779
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select CLK_R8A7790 if ARCH_R8A7790
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@ -47,6 +50,10 @@ config CLK_RZA1
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bool "RZ/A1H clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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config CLK_R7S9210
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bool "RZ/A2 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_R8A73A4
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bool "R-Mobile APE6 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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@ -69,6 +76,14 @@ config CLK_R8A77470
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bool "RZ/G1C clock support" if COMPILE_TEST
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select CLK_RCAR_GEN2_CPG
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config CLK_R8A774A1
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bool "RZ/G2M clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A774C0
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bool "RZ/G2E clock support" if COMPILE_TEST
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select CLK_RCAR_GEN3_CPG
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config CLK_R8A7778
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bool "R-Car M1A clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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@ -2,11 +2,14 @@
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# SoC
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obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
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obj-$(CONFIG_CLK_RZA1) += clk-rz.o
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obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
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@ -0,0 +1,217 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R7S9210 Clock Pulse Generator / Module Standby
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2018 Chris Brandt
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define CPG_FRQCR 0x00
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static u8 cpg_mode;
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/* Internal Clock ratio table */
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static const struct {
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unsigned int i;
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unsigned int g;
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unsigned int b;
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unsigned int p1;
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/* p0 is always 32 */;
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} ratio_tab[5] = { /* I, G, B, P1 */
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{ 2, 4, 8, 16}, /* FRQCR = 0x012 */
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{ 4, 4, 8, 16}, /* FRQCR = 0x112 */
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{ 8, 4, 8, 16}, /* FRQCR = 0x212 */
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{ 16, 8, 16, 16}, /* FRQCR = 0x322 */
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{ 16, 16, 32, 32}, /* FRQCR = 0x333 */
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};
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enum rz_clk_types {
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CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_RZA_PLL,
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R7S9210_CLK_P0,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static struct cpg_core_clk r7s9210_early_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
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DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
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/* Core Clock Outputs */
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DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
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};
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static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
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DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
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};
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static struct cpg_core_clk r7s9210_core_clks[] = {
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/* Core Clock Outputs */
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DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
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DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
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DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
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DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
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DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
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};
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static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
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DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C),
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DEF_MOD_STB("ether1", 64, R7S9210_CLK_B),
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DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),
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DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
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DEF_MOD_STB("spi2", 95, R7S9210_CLK_P1),
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DEF_MOD_STB("spi1", 96, R7S9210_CLK_P1),
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DEF_MOD_STB("spi0", 97, R7S9210_CLK_P1),
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};
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/* The clock dividers in the table vary based on DT and register settings */
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static void __init r7s9210_update_clk_table(struct clk *extal_clk,
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void __iomem *base)
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{
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int i;
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u16 frqcr;
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u8 index;
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/* If EXTAL is above 12MHz, then we know it is Mode 1 */
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if (clk_get_rate(extal_clk) > 12000000)
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cpg_mode = 1;
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frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
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if (frqcr == 0x012)
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index = 0;
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else if (frqcr == 0x112)
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index = 1;
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else if (frqcr == 0x212)
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index = 2;
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else if (frqcr == 0x322)
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index = 3;
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else if (frqcr == 0x333)
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index = 4;
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else
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BUG_ON(1); /* Illegal FRQCR value */
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for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
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switch (r7s9210_core_clks[i].id) {
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case R7S9210_CLK_I:
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r7s9210_core_clks[i].div = ratio_tab[index].i;
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break;
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case R7S9210_CLK_G:
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r7s9210_core_clks[i].div = ratio_tab[index].g;
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break;
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case R7S9210_CLK_B:
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r7s9210_core_clks[i].div = ratio_tab[index].b;
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break;
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case R7S9210_CLK_P1:
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case R7S9210_CLK_P1C:
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r7s9210_core_clks[i].div = ratio_tab[index].p1;
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break;
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case R7S9210_CLK_P0:
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r7s9210_core_clks[i].div = 32;
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break;
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}
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}
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}
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struct clk * __init rza2_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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parent = clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->id) {
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case CLK_MAIN:
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break;
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case CLK_PLL:
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if (cpg_mode)
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mult = 44; /* Divider 1 is 1/2 */
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else
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mult = 88; /* Divider 1 is 1 */
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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if (core->id == CLK_MAIN)
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r7s9210_update_clk_table(parent, base);
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
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/* Early Clocks */
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.early_core_clks = r7s9210_early_core_clks,
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.num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
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.early_mod_clks = r7s9210_early_mod_clks,
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.num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),
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/* Core Clocks */
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.core_clks = r7s9210_core_clks,
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.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r7s9210_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
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.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */
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/* Callbacks */
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.cpg_clk_register = rza2_cpg_clk_register,
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/* RZ/A2 has Standby Control Registers */
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.stbyctrl = true,
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};
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static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
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{
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cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
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}
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CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
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r7s9210_cpg_mssr_early_init);
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@ -8,6 +8,7 @@
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a7743-cpg-mssr.h>
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@ -34,7 +35,7 @@ enum clk_ids {
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
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static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("usb_extal", CLK_USB_EXTAL),
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@ -235,6 +236,8 @@ static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
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static int __init r8a7743_cpg_mssr_init(struct device *dev)
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{
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const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
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struct device_node *np = dev->of_node;
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unsigned int i;
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u32 cpg_mode;
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int error;
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@ -244,6 +247,14 @@ static int __init r8a7743_cpg_mssr_init(struct device *dev)
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
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/* RZ/G1N uses a 1/5 divider for ZG */
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for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
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if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
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r8a7743_core_clks[i].div = 5;
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break;
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}
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}
|
||||
return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,323 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774a1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7796-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774A1_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A774A1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A774A1_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A774A1_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A774A1_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A774A1_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A774A1_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A774A1_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A774A1_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d2", R8A774A1_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774A1_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774A1_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774A1_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774A1_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774A1_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("csi0", R8A774A1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774A1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A774A1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A774A1_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
|
||||
DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A774A1_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774A1_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774A1_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774A1_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A774A1_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774A1_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774A1_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774A1_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A774A1_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A774A1_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A774A1_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774A1_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A774A1_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774A1_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A774A1_CLK_S0D3),
|
||||
DEF_MOD("hscif4", 516, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A774A1_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A774A1_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774A1_CLK_S0D12),
|
||||
DEF_MOD("fcpvd2", 601, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("fcpci0", 617, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("fcpcs", 619, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vspd2", 621, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774A1_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("csi20", 714, R8A774A1_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A774A1_CLK_CSI0),
|
||||
DEF_MOD("du2", 722, R8A774A1_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A774A1_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774A1_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774A1_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A774A1_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A774A1_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("gpio7", 905, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774A1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774A1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a774a1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a774a1_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774a1_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a774a1_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a774a1_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a774a1_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a774a1_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a774a1_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a774a1_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a774a1_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774c0 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a77990-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774C0_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL0D4,
|
||||
CLK_PLL0D8,
|
||||
CLK_PLL0D20,
|
||||
CLK_PLL0D24,
|
||||
CLK_PLL1D2,
|
||||
CLK_PE,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),
|
||||
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1),
|
||||
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1),
|
||||
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1),
|
||||
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1),
|
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1),
|
||||
DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("s0d1", R8A774C0_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d3", R8A774C0_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d6", R8A774C0_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d12", R8A774C0_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s0d24", R8A774C0_CLK_S0D24, CLK_S0, 24, 1),
|
||||
DEF_FIXED("s1d1", R8A774C0_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A774C0_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774C0_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774C0_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774C0_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774C0_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774C0_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074),
|
||||
DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078),
|
||||
DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774C0_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A774C0_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A774C0_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A774C0_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A774C0_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A774C0_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_DIV6P1("csi0", R8A774C0_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774C0_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
|
||||
DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774C0_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774C0_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774C0_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A774C0_CLK_S3D4C),
|
||||
DEF_MOD("sdif3", 311, R8A774C0_CLK_SD3),
|
||||
DEF_MOD("sdif1", 313, R8A774C0_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774C0_CLK_SD0),
|
||||
DEF_MOD("pcie0", 319, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774C0_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774C0_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A774C0_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774C0_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774C0_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac0", 502, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("hscif4", 516, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif3", 517, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif2", 518, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif1", 519, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A774C0_CLK_S3D1C),
|
||||
DEF_MOD("thermal", 522, R8A774C0_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774C0_CLK_S3D4C),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("vspd1", 622, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vspd0", 623, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vspb", 626, R8A774C0_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774C0_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci0", 703, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("csi40", 716, R8A774C0_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A774C0_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774C0_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774C0_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin5", 806, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A774C0_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A774C0_CLK_S3D2),
|
||||
|
||||
DEF_MOD("gpio6", 906, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774C0_CLK_S3D2),
|
||||
|
||||
DEF_MOD("i2c7", 1003, R8A774C0_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774C0_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a774c0_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/1 x100/3 x100/3
|
||||
* 1 48 x 1 x100/1 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static int __init r8a774c0_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, 0, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774c0_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a774c0_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a774c0_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a774c0_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a774c0_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a774c0_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a774c0_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a774c0_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -70,6 +70,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
|
|
@ -108,8 +110,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
|
|||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
|
@ -280,25 +281,25 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
|
|||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
|
|
@ -306,23 +307,23 @@ static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
|
|||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct soc_device_attribute r8a7795es1[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -70,6 +70,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
|
|
@ -107,8 +109,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
|
@ -252,25 +253,25 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
|
|||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
|
|
@ -278,23 +279,23 @@ static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
|
|||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
|
|
@ -104,13 +106,13 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
||||
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
|
||||
|
|
@ -192,6 +194,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
|||
DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
|
||||
|
||||
|
|
@ -252,25 +255,25 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
|
|||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
|
|
@ -278,23 +281,23 @@ static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
|
|||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a77965_cpg_mssr_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -2,13 +2,14 @@
|
|||
/*
|
||||
* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017 Cogent Embedded Inc.
|
||||
* Copyright (C) 2017-2018 Cogent Embedded Inc.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -19,6 +20,13 @@
|
|||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
#define CPG_SD0CKCR 0x0074
|
||||
|
||||
enum r8a77970_clk_types {
|
||||
CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
|
||||
CLK_TYPE_R8A77970_SD0,
|
||||
};
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
|
||||
|
|
@ -39,6 +47,20 @@ enum clk_ids {
|
|||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static spinlock_t cpg_lock;
|
||||
|
||||
static const struct clk_div_table cpg_sd0h_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd0_div_table[] = {
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
|
|
@ -65,6 +87,10 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
|
|||
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
|
||||
|
||||
DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
|
||||
CLK_PLL1_DIV2),
|
||||
DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
|
|
@ -77,6 +103,11 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
|
||||
DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
|
||||
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
|
||||
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
|
||||
|
|
@ -89,6 +120,12 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
|
|||
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
|
||||
DEF_MOD("cmt3", 300, R8A77970_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77970_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77970_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77970_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
|
||||
DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
|
||||
DEF_MOD("rwdt", 402, R8A77970_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
|
||||
|
|
@ -170,11 +207,46 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
spin_lock_init(&cpg_lock);
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base,
|
||||
struct raw_notifier_head *notifiers)
|
||||
{
|
||||
const struct clk_div_table *table;
|
||||
const struct clk *parent;
|
||||
unsigned int shift;
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_R8A77970_SD0H:
|
||||
table = cpg_sd0h_div_table;
|
||||
shift = 8;
|
||||
break;
|
||||
case CLK_TYPE_R8A77970_SD0:
|
||||
table = cpg_sd0_div_table;
|
||||
shift = 4;
|
||||
break;
|
||||
default:
|
||||
return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
|
||||
notifiers);
|
||||
}
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
return clk_register_divider_table(NULL, core->name,
|
||||
__clk_get_name(parent), 0,
|
||||
base + CPG_SD0CKCR,
|
||||
shift, 4, 0, table, &cpg_lock);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a77970_core_clks,
|
||||
|
|
@ -193,5 +265,5 @@ const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
|
|||
|
||||
/* Callbacks */
|
||||
.init = r8a77970_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
.cpg_clk_register = r8a77970_cpg_clk_register,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
|
|
@ -64,6 +65,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
|
|
@ -96,6 +98,9 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("canfd", R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77980_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77980_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A77980_CLK_OSC, CLK_EXTAL, 8),
|
||||
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
||||
|
|
@ -114,9 +119,14 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
|||
DEF_MOD("msiof0", 211, R8A77980_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77980_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77980_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
|
||||
DEF_MOD("rwdt", 402, R8A77980_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
|
||||
|
|
@ -171,23 +181,23 @@ static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
|
|||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL2 PLL1 PLL3
|
||||
* MD EXTAL PLL2 PLL1 PLL3 OSC
|
||||
* 14 13 (MHz)
|
||||
* --------------------------------------------------
|
||||
* 0 0 16.66 x 1 x240 x192 x192
|
||||
* 0 1 20 x 1 x200 x160 x160
|
||||
* 1 0 27 x 1 x148 x118 x118
|
||||
* 1 1 33.33 / 2 x240 x192 x192
|
||||
* --------------------------------------------------------
|
||||
* 0 0 16.66 x 1 x240 x192 x192 /16
|
||||
* 0 1 20 x 1 x200 x160 x160 /19
|
||||
* 1 0 27 x 1 x148 x118 x118 /26
|
||||
* 1 1 33.33 / 2 x240 x192 x192 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 118, 1, 118, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 118, 1, 118, 1, 26, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a77980_cpg_mssr_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -44,6 +44,8 @@ enum clk_ids {
|
|||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
|
|
@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
|
|
@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
|
|
@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
||||
|
|
@ -202,6 +210,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
|||
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
|
|
@ -241,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
|
|||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/4 x100/3 x100/3
|
||||
* 1 48 x 1 x100/4 x100/3 x58/3
|
||||
* 0 48 x 1 x100/1 x100/3 x100/3
|
||||
* 1 48 x 1 x100/1 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@ enum clk_ids {
|
|||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
|
|
@ -69,6 +71,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
|
|
@ -87,8 +93,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
|
|
@ -99,6 +105,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
|
||||
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -539,7 +539,8 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
|
|||
* several uarts attached to this divider, and changing this impacts
|
||||
* everyone.
|
||||
*/
|
||||
if (clk->index == R9A06G032_DIV_UART) {
|
||||
if (clk->index == R9A06G032_DIV_UART ||
|
||||
clk->index == R9A06G032_DIV_P2_PG) {
|
||||
pr_devel("%s div uart hack!\n", __func__);
|
||||
return clk_get_rate(hw->clk);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
* Copyright (C) 2015-2018 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
|
|
@ -28,6 +28,8 @@
|
|||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
|
||||
|
||||
struct cpg_simple_notifier {
|
||||
struct notifier_block nb;
|
||||
void __iomem *reg;
|
||||
|
|
@ -441,7 +443,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
|
||||
parent = clks[core->parent & 0xffff]; /* some types use high bits */
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
|
|
@ -521,7 +523,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
|
||||
if (clk_get_rate(clks[cpg_clk_extalr])) {
|
||||
parent = clks[cpg_clk_extalr];
|
||||
value |= BIT(15);
|
||||
value |= CPG_RCKCR_CKSEL;
|
||||
}
|
||||
|
||||
writel(value, csn->reg);
|
||||
|
|
@ -534,16 +536,14 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
parent = clks[cpg_clk_extalr];
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PE:
|
||||
case CLK_TYPE_GEN3_MDSEL:
|
||||
/*
|
||||
* Peripheral clock with a fixed divider, selectable between
|
||||
* clean and spread spectrum parents using MD12
|
||||
* Clock selectable between two parents and two fixed dividers
|
||||
* using a mode pin
|
||||
*/
|
||||
if (cpg_mode & BIT(12)) {
|
||||
/* Clean */
|
||||
if (cpg_mode & BIT(core->offset)) {
|
||||
div = core->div & 0xffff;
|
||||
} else {
|
||||
/* SCCG */
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
|
@ -560,6 +560,28 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
return cpg_z_clk_register(core->name, __clk_get_name(parent),
|
||||
base, CPG_FRQCRC_Z2FC_MASK);
|
||||
|
||||
case CLK_TYPE_GEN3_OSC:
|
||||
/*
|
||||
* Clock combining OSC EXTAL predivider and a fixed divider
|
||||
*/
|
||||
div = cpg_pll_config->osc_prediv * core->div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_RCKSEL:
|
||||
/*
|
||||
* Clock selectable between two parents and two fixed dividers
|
||||
* using RCKCR.CKSEL
|
||||
*/
|
||||
if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
|
||||
div = core->div & 0xffff;
|
||||
} else {
|
||||
parent = clks[core->parent >> 16];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
div = core->div >> 16;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
*
|
||||
* R-Car Gen3 Clock Pulse Generator
|
||||
*
|
||||
* Copyright (C) 2015-2016 Glider bvba
|
||||
* Copyright (C) 2015-2018 Glider bvba
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
||||
|
|
@ -17,19 +18,35 @@ enum rcar_gen3_clk_types {
|
|||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_R,
|
||||
CLK_TYPE_GEN3_PE,
|
||||
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN3_Z,
|
||||
CLK_TYPE_GEN3_Z2,
|
||||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
|
||||
/* SoC specific definitions start here */
|
||||
CLK_TYPE_GEN3_SOC_BASE,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
||||
_div_clean) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
|
||||
(_parent_sscg) << 16 | (_parent_clean), \
|
||||
.div = (_div_sscg) << 16 | (_div_clean))
|
||||
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
|
||||
_parent_clean, _div_clean)
|
||||
|
||||
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
|
||||
|
||||
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
|
||||
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
|
|
@ -37,6 +54,7 @@ struct rcar_gen3_cpg_pll_config {
|
|||
u8 pll1_div;
|
||||
u8 pll3_mult;
|
||||
u8 pll3_div;
|
||||
u8 osc_prediv;
|
||||
};
|
||||
|
||||
#define CPG_RCKCR 0x240
|
||||
|
|
|
|||
|
|
@ -70,6 +70,17 @@ static const u16 smstpcr[] = {
|
|||
|
||||
#define SMSTPCR(i) smstpcr[i]
|
||||
|
||||
/*
|
||||
* Standby Control Register offsets (RZ/A)
|
||||
* Base address is FRQCR register
|
||||
*/
|
||||
|
||||
static const u16 stbcr[] = {
|
||||
0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
|
||||
0x424, 0x428, 0x42C,
|
||||
};
|
||||
|
||||
#define STBCR(i) stbcr[i]
|
||||
|
||||
/*
|
||||
* Software Reset Register offsets
|
||||
|
|
@ -107,6 +118,7 @@ static const u16 srcr[] = {
|
|||
* @notifiers: Notifier chain to save/restore clock state for system resume
|
||||
* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
|
||||
* @smstpcr_saved[].val: Saved values of SMSTPCR[]
|
||||
* @stbyctrl: This device has Standby Control Registers
|
||||
*/
|
||||
struct cpg_mssr_priv {
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
|
|
@ -115,11 +127,13 @@ struct cpg_mssr_priv {
|
|||
struct device *dev;
|
||||
void __iomem *base;
|
||||
spinlock_t rmw_lock;
|
||||
struct device_node *np;
|
||||
|
||||
struct clk **clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
bool stbyctrl;
|
||||
|
||||
struct raw_notifier_head notifiers;
|
||||
struct {
|
||||
|
|
@ -128,6 +142,7 @@ struct cpg_mssr_priv {
|
|||
} smstpcr_saved[ARRAY_SIZE(smstpcr)];
|
||||
};
|
||||
|
||||
static struct cpg_mssr_priv *cpg_mssr_priv;
|
||||
|
||||
/**
|
||||
* struct mstp_clock - MSTP gating clock
|
||||
|
|
@ -159,16 +174,29 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
|
|||
enable ? "ON" : "OFF");
|
||||
spin_lock_irqsave(&priv->rmw_lock, flags);
|
||||
|
||||
value = readl(priv->base + SMSTPCR(reg));
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
writel(value, priv->base + SMSTPCR(reg));
|
||||
if (priv->stbyctrl) {
|
||||
value = readb(priv->base + STBCR(reg));
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
writeb(value, priv->base + STBCR(reg));
|
||||
|
||||
/* dummy read to ensure write has completed */
|
||||
readb(priv->base + STBCR(reg));
|
||||
barrier_data(priv->base + STBCR(reg));
|
||||
} else {
|
||||
value = readl(priv->base + SMSTPCR(reg));
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
writel(value, priv->base + SMSTPCR(reg));
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&priv->rmw_lock, flags);
|
||||
|
||||
if (!enable)
|
||||
if (!enable || priv->stbyctrl)
|
||||
return 0;
|
||||
|
||||
for (i = 1000; i > 0; --i) {
|
||||
|
|
@ -202,7 +230,10 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
|
|||
struct cpg_mssr_priv *priv = clock->priv;
|
||||
u32 value;
|
||||
|
||||
value = readl(priv->base + MSTPSR(clock->index / 32));
|
||||
if (priv->stbyctrl)
|
||||
value = readb(priv->base + STBCR(clock->index / 32));
|
||||
else
|
||||
value = readl(priv->base + MSTPSR(clock->index / 32));
|
||||
|
||||
return !(value & BIT(clock->index % 32));
|
||||
}
|
||||
|
|
@ -223,6 +254,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
|||
unsigned int idx;
|
||||
const char *type;
|
||||
struct clk *clk;
|
||||
int range_check;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_CORE:
|
||||
|
|
@ -237,8 +269,14 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
|||
|
||||
case CPG_MOD:
|
||||
type = "module";
|
||||
idx = MOD_CLK_PACK(clkidx);
|
||||
if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
|
||||
if (priv->stbyctrl) {
|
||||
idx = MOD_CLK_PACK_10(clkidx);
|
||||
range_check = 7 - (clkidx % 10);
|
||||
} else {
|
||||
idx = MOD_CLK_PACK(clkidx);
|
||||
range_check = 31 - (clkidx % 100);
|
||||
}
|
||||
if (range_check < 0 || idx >= priv->num_mod_clks) {
|
||||
dev_err(dev, "Invalid %s clock index %u\n", type,
|
||||
clkidx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
|
@ -280,7 +318,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
|
||||
clk = of_clk_get_by_name(priv->np, core->name);
|
||||
break;
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
|
|
@ -310,6 +348,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
|||
}
|
||||
break;
|
||||
|
||||
case CLK_TYPE_FR:
|
||||
clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,
|
||||
core->mult);
|
||||
break;
|
||||
|
||||
default:
|
||||
if (info->cpg_clk_register)
|
||||
clk = info->cpg_clk_register(dev, core, info,
|
||||
|
|
@ -638,11 +681,22 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
|
|||
|
||||
|
||||
static const struct of_device_id cpg_mssr_match[] = {
|
||||
#ifdef CONFIG_CLK_R7S9210
|
||||
{
|
||||
.compatible = "renesas,r7s9210-cpg-mssr",
|
||||
.data = &r7s9210_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7743
|
||||
{
|
||||
.compatible = "renesas,r8a7743-cpg-mssr",
|
||||
.data = &r8a7743_cpg_mssr_info,
|
||||
},
|
||||
/* RZ/G1N is (almost) identical to RZ/G1M w.r.t. clocks. */
|
||||
{
|
||||
.compatible = "renesas,r8a7744-cpg-mssr",
|
||||
.data = &r8a7743_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7745
|
||||
{
|
||||
|
|
@ -656,6 +710,18 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a77470_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774A1
|
||||
{
|
||||
.compatible = "renesas,r8a774a1-cpg-mssr",
|
||||
.data = &r8a774a1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774C0
|
||||
{
|
||||
.compatible = "renesas,r8a774c0-cpg-mssr",
|
||||
.data = &r8a774c0_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7790
|
||||
{
|
||||
.compatible = "renesas,r8a7790-cpg-mssr",
|
||||
|
|
@ -777,13 +843,23 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
if (!mask)
|
||||
continue;
|
||||
|
||||
oldval = readl(priv->base + SMSTPCR(reg));
|
||||
if (priv->stbyctrl)
|
||||
oldval = readb(priv->base + STBCR(reg));
|
||||
else
|
||||
oldval = readl(priv->base + SMSTPCR(reg));
|
||||
newval = oldval & ~mask;
|
||||
newval |= priv->smstpcr_saved[reg].val & mask;
|
||||
if (newval == oldval)
|
||||
continue;
|
||||
|
||||
writel(newval, priv->base + SMSTPCR(reg));
|
||||
if (priv->stbyctrl) {
|
||||
writeb(newval, priv->base + STBCR(reg));
|
||||
/* dummy read to ensure write has completed */
|
||||
readb(priv->base + STBCR(reg));
|
||||
barrier_data(priv->base + STBCR(reg));
|
||||
continue;
|
||||
} else
|
||||
writel(newval, priv->base + SMSTPCR(reg));
|
||||
|
||||
/* Wait until enabled clocks are really enabled */
|
||||
mask &= ~priv->smstpcr_saved[reg].val;
|
||||
|
|
@ -814,61 +890,115 @@ static const struct dev_pm_ops cpg_mssr_pm = {
|
|||
#define DEV_PM_OPS NULL
|
||||
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
|
||||
|
||||
static int __init cpg_mssr_probe(struct platform_device *pdev)
|
||||
static int __init cpg_mssr_common_init(struct device *dev,
|
||||
struct device_node *np,
|
||||
const struct cpg_mssr_info *info)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct cpg_mssr_info *info;
|
||||
struct cpg_mssr_priv *priv;
|
||||
struct clk **clks = NULL;
|
||||
unsigned int nclks, i;
|
||||
struct resource *res;
|
||||
struct clk **clks;
|
||||
int error;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
if (info->init) {
|
||||
error = info->init(dev);
|
||||
if (error)
|
||||
return error;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->np = np;
|
||||
priv->dev = dev;
|
||||
spin_lock_init(&priv->rmw_lock);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
priv->base = of_iomap(np, 0);
|
||||
if (!priv->base) {
|
||||
error = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks) {
|
||||
error = -ENOMEM;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
dev_set_drvdata(dev, priv);
|
||||
cpg_mssr_priv = priv;
|
||||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
|
||||
priv->stbyctrl = info->stbyctrl;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
goto out_err;
|
||||
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
kfree(clks);
|
||||
if (priv->base)
|
||||
iounmap(priv->base);
|
||||
kfree(priv);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
void __init cpg_mssr_early_init(struct device_node *np,
|
||||
const struct cpg_mssr_info *info)
|
||||
{
|
||||
int error;
|
||||
int i;
|
||||
|
||||
error = cpg_mssr_common_init(NULL, np, info);
|
||||
if (error)
|
||||
return;
|
||||
|
||||
for (i = 0; i < info->num_early_core_clks; i++)
|
||||
cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
|
||||
cpg_mssr_priv);
|
||||
|
||||
for (i = 0; i < info->num_early_mod_clks; i++)
|
||||
cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
|
||||
cpg_mssr_priv);
|
||||
|
||||
}
|
||||
|
||||
static int __init cpg_mssr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct cpg_mssr_info *info;
|
||||
struct cpg_mssr_priv *priv;
|
||||
unsigned int i;
|
||||
int error;
|
||||
|
||||
info = of_device_get_match_data(dev);
|
||||
|
||||
if (!cpg_mssr_priv) {
|
||||
error = cpg_mssr_common_init(dev, dev->of_node, info);
|
||||
if (error)
|
||||
return error;
|
||||
}
|
||||
|
||||
priv = cpg_mssr_priv;
|
||||
priv->dev = dev;
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
for (i = 0; i < info->num_core_clks; i++)
|
||||
cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
|
||||
|
||||
for (i = 0; i < info->num_mod_clks; i++)
|
||||
cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
|
||||
|
||||
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = devm_add_action_or_reset(dev,
|
||||
cpg_mssr_del_clk_provider,
|
||||
np);
|
||||
|
|
@ -880,6 +1010,10 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
/* Reset Controller not supported for Standby Control SoCs */
|
||||
if (info->stbyctrl)
|
||||
return 0;
|
||||
|
||||
error = cpg_mssr_reset_controller_register(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ enum clk_types {
|
|||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
|
||||
CLK_TYPE_FR, /* Fixed Rate Clock */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
|
|
@ -53,6 +54,8 @@ enum clk_types {
|
|||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
#define DEF_RATE(_name, _id, _rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
|
|
@ -72,12 +75,24 @@ struct mssr_mod_clk {
|
|||
#define DEF_MOD(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
|
||||
|
||||
/* Convert from sparse base-10 to packed index space */
|
||||
#define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
|
||||
|
||||
#define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
|
||||
|
||||
#define DEF_MOD_STB(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
|
||||
|
||||
struct device_node;
|
||||
|
||||
/**
|
||||
* SoC-specific CPG/MSSR Description
|
||||
*
|
||||
* @early_core_clks: Array of Early Core Clock definitions
|
||||
* @num_early_core_clks: Number of entries in early_core_clks[]
|
||||
* @early_mod_clks: Array of Early Module Clock definitions
|
||||
* @num_early_mod_clks: Number of entries in early_mod_clks[]
|
||||
*
|
||||
* @core_clks: Array of Core Clock definitions
|
||||
* @num_core_clks: Number of entries in core_clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
|
|
@ -97,14 +112,25 @@ struct device_node;
|
|||
*
|
||||
* @init: Optional callback to perform SoC-specific initialization
|
||||
* @cpg_clk_register: Optional callback to handle special Core Clock types
|
||||
*
|
||||
* @stbyctrl: This device has Standby Control Registers which are 8-bits
|
||||
* wide, no status registers (MSTPSR) and have different address
|
||||
* offsets.
|
||||
*/
|
||||
|
||||
struct cpg_mssr_info {
|
||||
/* Early Clocks */
|
||||
const struct cpg_core_clk *early_core_clks;
|
||||
unsigned int num_early_core_clks;
|
||||
const struct mssr_mod_clk *early_mod_clks;
|
||||
unsigned int num_early_mod_clks;
|
||||
|
||||
/* Core Clocks */
|
||||
const struct cpg_core_clk *core_clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
bool stbyctrl;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct mssr_mod_clk *mod_clks;
|
||||
|
|
@ -128,9 +154,12 @@ struct cpg_mssr_info {
|
|||
struct raw_notifier_head *notifiers);
|
||||
};
|
||||
|
||||
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
|
||||
|
|
@ -143,6 +172,8 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
|
||||
|
||||
void __init cpg_mssr_early_init(struct device_node *np,
|
||||
const struct cpg_mssr_info *info);
|
||||
|
||||
/*
|
||||
* Helpers for fixing up clock tables depending on SoC revision
|
||||
|
|
|
|||
|
|
@ -1,10 +1,7 @@
|
|||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R7S9210 CPG Core Clocks */
|
||||
#define R7S9210_CLK_I 0
|
||||
#define R7S9210_CLK_G 1
|
||||
#define R7S9210_CLK_B 2
|
||||
#define R7S9210_CLK_P1 3
|
||||
#define R7S9210_CLK_P1C 4
|
||||
#define R7S9210_CLK_P0 5
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */
|
||||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a7744 CPG Core Clocks */
|
||||
#define R8A7744_CLK_Z 0
|
||||
#define R8A7744_CLK_ZG 1
|
||||
#define R8A7744_CLK_ZTR 2
|
||||
#define R8A7744_CLK_ZTRD2 3
|
||||
#define R8A7744_CLK_ZT 4
|
||||
#define R8A7744_CLK_ZX 5
|
||||
#define R8A7744_CLK_ZS 6
|
||||
#define R8A7744_CLK_HP 7
|
||||
#define R8A7744_CLK_B 9
|
||||
#define R8A7744_CLK_LB 10
|
||||
#define R8A7744_CLK_P 11
|
||||
#define R8A7744_CLK_CL 12
|
||||
#define R8A7744_CLK_M2 13
|
||||
#define R8A7744_CLK_ZB3 15
|
||||
#define R8A7744_CLK_ZB3D2 16
|
||||
#define R8A7744_CLK_DDR 17
|
||||
#define R8A7744_CLK_SDH 18
|
||||
#define R8A7744_CLK_SD0 19
|
||||
#define R8A7744_CLK_SD2 20
|
||||
#define R8A7744_CLK_SD3 21
|
||||
#define R8A7744_CLK_MMC0 22
|
||||
#define R8A7744_CLK_MP 23
|
||||
#define R8A7744_CLK_QSPI 26
|
||||
#define R8A7744_CLK_CP 27
|
||||
#define R8A7744_CLK_RCAN 28
|
||||
#define R8A7744_CLK_R 29
|
||||
#define R8A7744_CLK_OSC 30
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */
|
||||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2016 Cogent Embedded Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -0,0 +1,58 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774a1 CPG Core Clocks */
|
||||
#define R8A774A1_CLK_Z 0
|
||||
#define R8A774A1_CLK_Z2 1
|
||||
#define R8A774A1_CLK_ZG 2
|
||||
#define R8A774A1_CLK_ZTR 3
|
||||
#define R8A774A1_CLK_ZTRD2 4
|
||||
#define R8A774A1_CLK_ZT 5
|
||||
#define R8A774A1_CLK_ZX 6
|
||||
#define R8A774A1_CLK_S0D1 7
|
||||
#define R8A774A1_CLK_S0D2 8
|
||||
#define R8A774A1_CLK_S0D3 9
|
||||
#define R8A774A1_CLK_S0D4 10
|
||||
#define R8A774A1_CLK_S0D6 11
|
||||
#define R8A774A1_CLK_S0D8 12
|
||||
#define R8A774A1_CLK_S0D12 13
|
||||
#define R8A774A1_CLK_S1D2 14
|
||||
#define R8A774A1_CLK_S1D4 15
|
||||
#define R8A774A1_CLK_S2D1 16
|
||||
#define R8A774A1_CLK_S2D2 17
|
||||
#define R8A774A1_CLK_S2D4 18
|
||||
#define R8A774A1_CLK_S3D1 19
|
||||
#define R8A774A1_CLK_S3D2 20
|
||||
#define R8A774A1_CLK_S3D4 21
|
||||
#define R8A774A1_CLK_LB 22
|
||||
#define R8A774A1_CLK_CL 23
|
||||
#define R8A774A1_CLK_ZB3 24
|
||||
#define R8A774A1_CLK_ZB3D2 25
|
||||
#define R8A774A1_CLK_ZB3D4 26
|
||||
#define R8A774A1_CLK_CR 27
|
||||
#define R8A774A1_CLK_CRD2 28
|
||||
#define R8A774A1_CLK_SD0H 29
|
||||
#define R8A774A1_CLK_SD0 30
|
||||
#define R8A774A1_CLK_SD1H 31
|
||||
#define R8A774A1_CLK_SD1 32
|
||||
#define R8A774A1_CLK_SD2H 33
|
||||
#define R8A774A1_CLK_SD2 34
|
||||
#define R8A774A1_CLK_SD3H 35
|
||||
#define R8A774A1_CLK_SD3 36
|
||||
#define R8A774A1_CLK_RPC 37
|
||||
#define R8A774A1_CLK_RPCD2 38
|
||||
#define R8A774A1_CLK_MSO 39
|
||||
#define R8A774A1_CLK_HDMI 40
|
||||
#define R8A774A1_CLK_CSI0 41
|
||||
#define R8A774A1_CLK_CP 42
|
||||
#define R8A774A1_CLK_CPEX 43
|
||||
#define R8A774A1_CLK_R 44
|
||||
#define R8A774A1_CLK_OSC 45
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774c0 CPG Core Clocks */
|
||||
#define R8A774C0_CLK_Z2 0
|
||||
#define R8A774C0_CLK_ZG 1
|
||||
#define R8A774C0_CLK_ZTR 2
|
||||
#define R8A774C0_CLK_ZT 3
|
||||
#define R8A774C0_CLK_ZX 4
|
||||
#define R8A774C0_CLK_S0D1 5
|
||||
#define R8A774C0_CLK_S0D3 6
|
||||
#define R8A774C0_CLK_S0D6 7
|
||||
#define R8A774C0_CLK_S0D12 8
|
||||
#define R8A774C0_CLK_S0D24 9
|
||||
#define R8A774C0_CLK_S1D1 10
|
||||
#define R8A774C0_CLK_S1D2 11
|
||||
#define R8A774C0_CLK_S1D4 12
|
||||
#define R8A774C0_CLK_S2D1 13
|
||||
#define R8A774C0_CLK_S2D2 14
|
||||
#define R8A774C0_CLK_S2D4 15
|
||||
#define R8A774C0_CLK_S3D1 16
|
||||
#define R8A774C0_CLK_S3D2 17
|
||||
#define R8A774C0_CLK_S3D4 18
|
||||
#define R8A774C0_CLK_S0D6C 19
|
||||
#define R8A774C0_CLK_S3D1C 20
|
||||
#define R8A774C0_CLK_S3D2C 21
|
||||
#define R8A774C0_CLK_S3D4C 22
|
||||
#define R8A774C0_CLK_LB 23
|
||||
#define R8A774C0_CLK_CL 24
|
||||
#define R8A774C0_CLK_ZB3 25
|
||||
#define R8A774C0_CLK_ZB3D2 26
|
||||
#define R8A774C0_CLK_CR 27
|
||||
#define R8A774C0_CLK_CRD2 28
|
||||
#define R8A774C0_CLK_SD0H 29
|
||||
#define R8A774C0_CLK_SD0 30
|
||||
#define R8A774C0_CLK_SD1H 31
|
||||
#define R8A774C0_CLK_SD1 32
|
||||
#define R8A774C0_CLK_SD3H 33
|
||||
#define R8A774C0_CLK_SD3 34
|
||||
#define R8A774C0_CLK_RPC 35
|
||||
#define R8A774C0_CLK_RPCD2 36
|
||||
#define R8A774C0_CLK_ZA2 37
|
||||
#define R8A774C0_CLK_ZA8 38
|
||||
#define R8A774C0_CLK_Z2D 39
|
||||
#define R8A774C0_CLK_MSO 40
|
||||
#define R8A774C0_CLK_R 41
|
||||
#define R8A774C0_CLK_OSC 42
|
||||
#define R8A774C0_CLK_LV0 43
|
||||
#define R8A774C0_CLK_LV1 44
|
||||
#define R8A774C0_CLK_CSI0 45
|
||||
#define R8A774C0_CLK_CP 46
|
||||
#define R8A774C0_CLK_CPEX 47
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
|
||||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,16 +1,8 @@
|
|||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* r8a7793 clock definition
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,11 +1,7 @@
|
|||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
|
|
|
|||
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
|
||||
|
|
|
|||
Loading…
Reference in New Issue