drm/radeon/kms: blit code commoning
factor out most of evergreen blit code and use the refactored code from r600 that is now common for both r600 and evergreen Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ilija Hadzic
Dave Airlie
parent
b353096345
commit
fb3d9e97e1
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@ -3087,7 +3087,7 @@ static int evergreen_startup(struct radeon_device *rdev)
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r = evergreen_blit_init(rdev);
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if (r) {
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evergreen_blit_fini(rdev);
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r600_blit_fini(rdev);
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rdev->asic->copy = NULL;
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dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
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}
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@ -3172,27 +3172,6 @@ int evergreen_suspend(struct radeon_device *rdev)
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return 0;
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}
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int evergreen_copy_blit(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_pages, struct radeon_fence *fence)
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{
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int r;
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mutex_lock(&rdev->r600_blit.mutex);
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rdev->r600_blit.vb_ib = NULL;
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r = evergreen_blit_prepare_copy(rdev, num_pages);
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if (r) {
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if (rdev->r600_blit.vb_ib)
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radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
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mutex_unlock(&rdev->r600_blit.mutex);
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return r;
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}
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evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages);
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evergreen_blit_done_copy(rdev, fence);
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mutex_unlock(&rdev->r600_blit.mutex);
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return 0;
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}
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/* Plan is to move initialization in that function and use
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* helper function so that radeon_device_init pretty much
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* do nothing more than calling asic specific function. This
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@ -3301,7 +3280,7 @@ int evergreen_init(struct radeon_device *rdev)
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void evergreen_fini(struct radeon_device *rdev)
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{
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evergreen_blit_fini(rdev);
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r600_blit_fini(rdev);
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r700_cp_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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@ -44,10 +44,6 @@
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#define COLOR_5_6_5 0x8
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#define COLOR_8_8_8_8 0x1a
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#define RECT_UNIT_H 32
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#define RECT_UNIT_W (RADEON_GPU_PAGE_SIZE / 4 / RECT_UNIT_H)
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#define MAX_RECT_DIM 16384
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/* emits 17 */
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static void
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set_render_target(struct radeon_device *rdev, int format,
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@ -599,31 +595,6 @@ set_default_state(struct radeon_device *rdev)
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}
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static uint32_t i2f(uint32_t input)
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{
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u32 result, i, exponent, fraction;
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if ((input & 0x3fff) == 0)
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result = 0; /* 0 is a special case */
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else {
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exponent = 140; /* exponent biased by 127; */
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fraction = (input & 0x3fff) << 10; /* cheat and only
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handle numbers below 2^^15 */
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for (i = 0; i < 14; i++) {
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if (fraction & 0x800000)
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break;
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else {
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fraction = fraction << 1; /* keep
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shifting left until top bit = 1 */
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exponent = exponent - 1;
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}
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}
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result = exponent << 23 | (fraction & 0x7fffff); /* mask
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off top bit; assumed 1 */
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}
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return result;
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}
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int evergreen_blit_init(struct radeon_device *rdev)
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{
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u32 obj_size;
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@ -632,6 +603,24 @@ int evergreen_blit_init(struct radeon_device *rdev)
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u32 packet2s[16];
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int num_packet2s = 0;
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rdev->r600_blit.primitives.set_render_target = set_render_target;
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rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync;
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rdev->r600_blit.primitives.set_shaders = set_shaders;
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rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource;
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rdev->r600_blit.primitives.set_tex_resource = set_tex_resource;
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rdev->r600_blit.primitives.set_scissors = set_scissors;
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rdev->r600_blit.primitives.draw_auto = draw_auto;
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rdev->r600_blit.primitives.set_default_state = set_default_state;
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rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
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rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
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rdev->r600_blit.ring_size_common += 5; /* done copy */
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rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
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rdev->r600_blit.ring_size_per_loop = 74;
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rdev->r600_blit.max_dim = 16384;
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/* pin copy shader into vram if already initialized */
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if (rdev->r600_blit.shader_obj)
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goto done;
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@ -727,216 +716,3 @@ done:
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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void evergreen_blit_fini(struct radeon_device *rdev)
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{
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int r;
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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if (rdev->r600_blit.shader_obj == NULL)
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return;
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/* If we can't reserve the bo, unref should be enough to destroy
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* it when it becomes idle.
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*/
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r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
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if (!r) {
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radeon_bo_unpin(rdev->r600_blit.shader_obj);
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radeon_bo_unreserve(rdev->r600_blit.shader_obj);
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}
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radeon_bo_unref(&rdev->r600_blit.shader_obj);
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}
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static int evergreen_vb_ib_get(struct radeon_device *rdev)
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{
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int r;
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r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
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if (r) {
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DRM_ERROR("failed to get IB for vertex buffer\n");
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return r;
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}
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rdev->r600_blit.vb_total = 64*1024;
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rdev->r600_blit.vb_used = 0;
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return 0;
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}
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static void evergreen_vb_ib_put(struct radeon_device *rdev)
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{
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radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
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radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
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}
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/* maps the rectangle to the buffer so that satisfies the following properties:
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* - dimensions are less or equal to the hardware limit (MAX_RECT_DIM)
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* - rectangle consists of integer number of pages
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* - height is an integer multiple of RECT_UNIT_H
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* - width is an integer multiple of RECT_UNIT_W
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* - (the above three conditions also guarantee tile-aligned size)
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* - it is as square as possible (sides ratio never greater than 2:1)
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* - uses maximum number of pages that fit the above constraints
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*
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* input: buffer size, pointers to width/height variables
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* return: number of pages that were successfully mapped to the rectangle
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* width/height of the rectangle
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*/
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static unsigned evergreen_blit_create_rect(unsigned num_pages, int *width, int *height)
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{
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unsigned max_pages;
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unsigned pages = num_pages;
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int w, h;
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if (num_pages == 0) {
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/* not supposed to be called with no pages, but just in case */
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h = 0;
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w = 0;
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pages = 0;
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WARN_ON(1);
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} else {
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int rect_order = 2;
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h = RECT_UNIT_H;
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while (num_pages / rect_order) {
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h *= 2;
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rect_order *= 4;
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if (h >= MAX_RECT_DIM) {
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h = MAX_RECT_DIM;
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break;
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}
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}
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max_pages = (MAX_RECT_DIM * h) / (RECT_UNIT_W * RECT_UNIT_H);
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if (pages > max_pages)
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pages = max_pages;
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w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
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w = (w / RECT_UNIT_W) * RECT_UNIT_W;
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pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
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BUG_ON(pages == 0);
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}
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DRM_DEBUG("blit_rectangle: h=%d, w=%d, pages=%d\n", h, w, pages);
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/* return width and height only of the caller wants it */
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if (height)
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*height = h;
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if (width)
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*width = w;
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return pages;
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}
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int evergreen_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages)
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{
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int r;
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int ring_size;
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/* loops of emits + fence emit possible */
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int dwords_per_loop = 74, num_loops = 0;
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r = evergreen_vb_ib_get(rdev);
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if (r)
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return r;
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/* num loops */
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while (num_pages) {
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num_pages -= evergreen_blit_create_rect(num_pages, NULL, NULL);
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num_loops++;
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}
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/* calculate number of loops correctly */
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 55; /* shaders + def state */
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ring_size += 10; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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ring_size += 10; /* fence emit for done copy */
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r = radeon_ring_lock(rdev, ring_size);
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if (r)
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return r;
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set_default_state(rdev); /* 36 */
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set_shaders(rdev); /* 16 */
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return 0;
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}
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void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
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{
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int r;
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if (rdev->r600_blit.vb_ib)
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evergreen_vb_ib_put(rdev);
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if (fence)
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r = radeon_fence_emit(rdev, fence);
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radeon_ring_unlock_commit(rdev);
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}
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void evergreen_kms_blit_copy(struct radeon_device *rdev,
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u64 src_gpu_addr, u64 dst_gpu_addr,
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unsigned num_pages)
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{
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u64 vb_gpu_addr;
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u32 *vb;
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DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
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num_pages, rdev->r600_blit.vb_used);
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vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
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while (num_pages) {
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int w, h;
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unsigned size_in_bytes;
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unsigned pages_per_loop = evergreen_blit_create_rect(num_pages, &w, &h);
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size_in_bytes = pages_per_loop * RADEON_GPU_PAGE_SIZE;
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DRM_DEBUG("rectangle w=%d h=%d\n", w, h);
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if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
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WARN_ON(1);
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}
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vb[0] = 0;
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vb[1] = 0;
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vb[2] = 0;
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vb[3] = 0;
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vb[4] = 0;
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vb[5] = i2f(h);
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vb[6] = 0;
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vb[7] = i2f(h);
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vb[8] = i2f(w);
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vb[9] = i2f(h);
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vb[10] = i2f(w);
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vb[11] = i2f(h);
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/* src 10 */
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set_tex_resource(rdev, FMT_8_8_8_8, w, h, w, src_gpu_addr);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_TC_ACTION_ENA, size_in_bytes, src_gpu_addr);
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/* dst 17 */
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set_render_target(rdev, COLOR_8_8_8_8, w, h, dst_gpu_addr);
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/* scissors 12 */
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set_scissors(rdev, 0, 0, w, h);
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/* Vertex buffer setup 15 */
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vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
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set_vtx_resource(rdev, vb_gpu_addr);
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/* draw 10 */
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draw_auto(rdev);
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/* 5 */
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cp_set_surface_sync(rdev,
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PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
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size_in_bytes, dst_gpu_addr);
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/* 74 ring dwords per loop */
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vb += 12;
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rdev->r600_blit.vb_used += 4*12;
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src_gpu_addr += size_in_bytes;
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dst_gpu_addr += size_in_bytes;
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num_pages -= pages_per_loop;
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}
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}
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@ -1401,7 +1401,7 @@ static int cayman_startup(struct radeon_device *rdev)
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r = evergreen_blit_init(rdev);
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if (r) {
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evergreen_blit_fini(rdev);
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r600_blit_fini(rdev);
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rdev->asic->copy = NULL;
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dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
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}
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@ -1589,7 +1589,7 @@ int cayman_init(struct radeon_device *rdev)
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void cayman_fini(struct radeon_device *rdev)
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{
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evergreen_blit_fini(rdev);
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r600_blit_fini(rdev);
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cayman_cp_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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@ -765,9 +765,9 @@ static struct radeon_asic evergreen_asic = {
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &evergreen_cs_parse,
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.copy_blit = &evergreen_copy_blit,
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.copy_blit = &r600_copy_blit,
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.copy_dma = NULL,
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.copy = &evergreen_copy_blit,
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.copy = &r600_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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@ -812,9 +812,9 @@ static struct radeon_asic sumo_asic = {
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &evergreen_cs_parse,
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.copy_blit = &evergreen_copy_blit,
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.copy_blit = &r600_copy_blit,
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.copy_dma = NULL,
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.copy = &evergreen_copy_blit,
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.copy = &r600_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = NULL,
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@ -859,9 +859,9 @@ static struct radeon_asic btc_asic = {
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &evergreen_cs_parse,
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.copy_blit = &evergreen_copy_blit,
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.copy_blit = &r600_copy_blit,
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.copy_dma = NULL,
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.copy = &evergreen_copy_blit,
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.copy = &r600_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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@ -906,9 +906,9 @@ static struct radeon_asic cayman_asic = {
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.get_vblank_counter = &evergreen_get_vblank_counter,
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.fence_ring_emit = &r600_fence_ring_emit,
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.cs_parse = &evergreen_cs_parse,
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.copy_blit = &evergreen_copy_blit,
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.copy_blit = &r600_copy_blit,
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.copy_dma = NULL,
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.copy = &evergreen_copy_blit,
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.copy = &r600_copy_blit,
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.get_engine_clock = &radeon_atom_get_engine_clock,
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.set_engine_clock = &radeon_atom_set_engine_clock,
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.get_memory_clock = &radeon_atom_get_memory_clock,
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@ -401,9 +401,6 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev);
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int evergreen_asic_reset(struct radeon_device *rdev);
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void evergreen_bandwidth_update(struct radeon_device *rdev);
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void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
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int evergreen_copy_blit(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_pages, struct radeon_fence *fence);
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void evergreen_hpd_init(struct radeon_device *rdev);
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void evergreen_hpd_fini(struct radeon_device *rdev);
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bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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@ -421,13 +418,6 @@ extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_ba
|
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extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
|
||||
void evergreen_disable_interrupt_state(struct radeon_device *rdev);
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||||
int evergreen_blit_init(struct radeon_device *rdev);
|
||||
void evergreen_blit_fini(struct radeon_device *rdev);
|
||||
/* evergreen blit */
|
||||
int evergreen_blit_prepare_copy(struct radeon_device *rdev, unsigned num_pages);
|
||||
void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
|
||||
void evergreen_kms_blit_copy(struct radeon_device *rdev,
|
||||
u64 src_gpu_addr, u64 dst_gpu_addr,
|
||||
unsigned num_pages);
|
||||
|
||||
/*
|
||||
* cayman
|
||||
|
|
|
|||
Loading…
Reference in a new issue